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-rw-r--r--board/zylonite/flash.c18
-rw-r--r--board/zylonite/lowlevel_init.S14
-rw-r--r--board/zylonite/nand.c20
3 files changed, 26 insertions, 26 deletions
diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c
index 80b520b..5ba84c6 100644
--- a/board/zylonite/flash.c
+++ b/board/zylonite/flash.c
@@ -28,7 +28,7 @@
#include <linux/byteorder/swab.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#define FLASH_PORT_WIDTH32
@@ -66,7 +66,7 @@ unsigned long flash_init (void)
int i;
ulong size = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -86,8 +86,8 @@ unsigned long flash_init (void)
/* Protect monitor and environment sectors
*/
flash_protect ( FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0] );
flash_protect ( FLAG_PROTECT_SET,
@@ -206,10 +206,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
break;
}
- if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CFG_MAX_FLASH_SECT);
- info->sector_count = CFG_MAX_FLASH_SECT;
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
@@ -279,7 +279,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -413,7 +413,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data)
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
index da01765..ff17c7e 100644
--- a/board/zylonite/lowlevel_init.S
+++ b/board/zylonite/lowlevel_init.S
@@ -29,7 +29,7 @@
#include <version.h>
#include <asm/arch/pxa-regs.h>
-DRAM_SIZE: .long CFG_DRAM_SIZE
+DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
@@ -235,13 +235,13 @@ mem_init:
orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
str r1, [r0]
-#ifndef CFG_SKIP_DRAM_SCRUB
+#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
/* scrub/init SDRAM if enabled/present */
-/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
-/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
+/* ldr r11, =0xa0000000 /\* base address of SDRAM (CONFIG_SYS_DRAM_BASE) *\/ */
+/* ldr r12, =0x04000000 /\* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) *\/ */
/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
- ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
- ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
+ ldr r8, =0xa0000000 /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
+ ldr r9, =0x04000000 /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
mov r0, #0 /* scrub with 0x0000:0000 */
mov r1, #0
mov r2, #0
@@ -255,7 +255,7 @@ mem_init:
stmia r8!, {r0-r7}
beq 15f
b 10b
-#endif /* CFG_SKIP_DRAM_SCRUB */
+#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
15:
/* Mask all interrupts */
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 7f22935..895fb2b 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -28,19 +28,19 @@
#include <nand.h>
#include <asm/arch/pxa-regs.h>
-#ifdef CFG_DFC_DEBUG1
+#ifdef CONFIG_SYS_DFC_DEBUG1
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
#else
# define DFC_DEBUG1(fmt, args...)
#endif
-#ifdef CFG_DFC_DEBUG2
+#ifdef CONFIG_SYS_DFC_DEBUG2
# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
#else
# define DFC_DEBUG2(fmt, args...)
#endif
-#ifdef CFG_DFC_DEBUG3
+#ifdef CONFIG_SYS_DFC_DEBUG3
# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
#else
# define DFC_DEBUG3(fmt, args...)
@@ -211,7 +211,7 @@ static void wait_us(unsigned long us)
static void dfc_clear_nddb(void)
{
NDCR &= ~NDCR_ND_RUN;
- wait_us(CFG_NAND_OTHER_TO);
+ wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
@@ -222,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event)
if(!event)
return 0xff000000;
else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
- timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+ timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
else
- timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+ timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
while(1) {
ndsr = NDSR;
@@ -247,7 +247,7 @@ static void dfc_new_cmd(void)
int retry = 0;
unsigned long status;
- while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+ while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
NDSR = 0xFFF;
@@ -438,8 +438,8 @@ int board_nand_init(struct nand_chip *nand)
/* turn on the NAND Controller Clock (104 MHz @ D0) */
CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
-#undef CFG_TIMING_TIGHT
-#ifndef CFG_TIMING_TIGHT
+#undef CONFIG_SYS_TIMING_TIGHT
+#ifndef CONFIG_SYS_TIMING_TIGHT
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
DFC_MAX_tCH);
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
@@ -478,7 +478,7 @@ int board_nand_init(struct nand_chip *nand)
DFC_MAX_tWHR);
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
DFC_MAX_tAR);
-#endif /* CFG_TIMING_TIGHT */
+#endif /* CONFIG_SYS_TIMING_TIGHT */
DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
generated by cgit v1.1 at 2024-11-25 16:25:55 +0000