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-rw-r--r--board/xsengine/flash.c12
-rw-r--r--board/xsengine/lowlevel_init.S68
-rw-r--r--board/xsengine/u-boot.lds2
3 files changed, 41 insertions, 41 deletions
diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c
index a188e24..736905a 100644
--- a/board/xsengine/flash.c
+++ b/board/xsengine/flash.c
@@ -29,7 +29,7 @@
#define SWAP(x) __swab32(x)
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Functions */
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
@@ -43,7 +43,7 @@ unsigned long flash_init (void)
int i;
ulong size = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
@@ -61,8 +61,8 @@ unsigned long flash_init (void)
}
/* Protect monitor and environment sectors */
- flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
- flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+ flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
+ flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
return size;
}
@@ -338,7 +338,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (vu_long*)(info->start[l_sect]);
while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -462,7 +462,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S
index b0b1561..0d94ab6 100644
--- a/board/xsengine/lowlevel_init.S
+++ b/board/xsengine/lowlevel_init.S
@@ -2,7 +2,7 @@
#include <version.h>
#include <asm/arch/pxa-regs.h>
-DRAM_SIZE: .long CFG_DRAM_SIZE
+DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
.globl lowlevel_init
lowlevel_init:
@@ -14,93 +14,93 @@ lowlevel_init:
/* General purpose set registers */
ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
+ ldr r1, =CONFIG_SYS_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
+ ldr r1, =CONFIG_SYS_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
+ ldr r1, =CONFIG_SYS_GPSR2_VAL
str r1, [r0]
/* General purpose clear registers */
ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
+ ldr r1, =CONFIG_SYS_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
+ ldr r1, =CONFIG_SYS_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
+ ldr r1, =CONFIG_SYS_GPCR2_VAL
str r1, [r0]
/* General rising edge registers */
ldr r0, =GRER0
- ldr r1, =CFG_GRER0_VAL
+ ldr r1, =CONFIG_SYS_GRER0_VAL
str r1, [r0]
ldr r0, =GRER1
- ldr r1, =CFG_GRER1_VAL
+ ldr r1, =CONFIG_SYS_GRER1_VAL
str r1, [r0]
ldr r0, =GRER2
- ldr r1, =CFG_GRER2_VAL
+ ldr r1, =CONFIG_SYS_GRER2_VAL
str r1, [r0]
/* General falling edge registers */
ldr r0, =GFER0
- ldr r1, =CFG_GFER0_VAL
+ ldr r1, =CONFIG_SYS_GFER0_VAL
str r1, [r0]
ldr r0, =GFER1
- ldr r1, =CFG_GFER1_VAL
+ ldr r1, =CONFIG_SYS_GFER1_VAL
str r1, [r0]
ldr r0, =GFER2
- ldr r1, =CFG_GFER2_VAL
+ ldr r1, =CONFIG_SYS_GFER2_VAL
str r1, [r0]
/* General edge detect registers */
ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
+ ldr r1, =CONFIG_SYS_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
+ ldr r1, =CONFIG_SYS_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
+ ldr r1, =CONFIG_SYS_GPDR2_VAL
str r1, [r0]
/* General alternate function registers */
ldr r0, =GAFR0_L /* [0:15] */
- ldr r1, =CFG_GAFR0_L_VAL
+ ldr r1, =CONFIG_SYS_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U /* [31:16] */
- ldr r1, =CFG_GAFR0_U_VAL
+ ldr r1, =CONFIG_SYS_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L /* [47:32] */
- ldr r1, =CFG_GAFR1_L_VAL
+ ldr r1, =CONFIG_SYS_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U /* [63:48] */
- ldr r1, =CFG_GAFR1_U_VAL
+ ldr r1, =CONFIG_SYS_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L /* [79:64] */
- ldr r1, =CFG_GAFR2_L_VAL
+ ldr r1, =CONFIG_SYS_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U /* [80] */
- ldr r1, =CFG_GAFR2_U_VAL
+ ldr r1, =CONFIG_SYS_GAFR2_U_VAL
str r1, [r0]
/* General purpose direction registers */
ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
+ ldr r1, =CONFIG_SYS_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
+ ldr r1, =CONFIG_SYS_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
+ ldr r1, =CONFIG_SYS_GPDR2_VAL
str r1, [r0]
/* Power manager sleep status */
ldr r0, =PSSR
- ldr r1, =CFG_PSSR_VAL
+ ldr r1, =CONFIG_SYS_PSSR_VAL
str r1, [r0]
/* ---- MEMORY INITIALISATION ---- */
@@ -121,17 +121,17 @@ mem_init:
/* ---- FLASH INITIALISATION ---- */
/* Write MSC0 and read back to ensure data change is accepted by cpu */
- ldr r2, =CFG_MSC0_VAL
+ ldr r2, =CONFIG_SYS_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET]
/* ---- SDRAM INITIALISATION ---- */
/* get the MDREFR settings */
- ldr r2, =CFG_MDREFR_VAL
+ ldr r2, =CONFIG_SYS_MDREFR_VAL
str r2, [r1, #MDREFR_OFFSET]
/* fetch platform value of MDCNFG */
- ldr r2, =CFG_MDCNFG_VAL
+ ldr r2, =CONFIG_SYS_MDCNFG_VAL
/* disable all sdram banks */
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
@@ -153,7 +153,7 @@ mem_init:
/* Access memory *not yet enabled* for CBR refresh cycles (8) */
/* CBR is generated for all banks */
- ldr r2, =CFG_DRAM_BASE
+ ldr r2, =CONFIG_SYS_DRAM_BASE
str r2, [r2]
str r2, [r2]
str r2, [r2]
@@ -172,7 +172,7 @@ mem_init:
str r2, [r1, #MDCNFG_OFFSET]
/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
- ldr r2, =CFG_MDMRS_VAL
+ ldr r2, =CONFIG_SYS_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
/* ---- INTERRUPT INITIALISATION ---- */
@@ -183,7 +183,7 @@ mem_init:
str r1, [r2]
/* Set interrupt mask register */
- ldr r1, =CFG_ICMR_VAL
+ ldr r1, =CONFIG_SYS_ICMR_VAL
ldr r2, =ICMR
str r1, [r2]
@@ -196,7 +196,7 @@ mem_init:
str r2, [r1]
/* set core clocks */
- ldr r2, =CFG_CCCR_VAL
+ ldr r2, =CONFIG_SYS_CCCR_VAL
ldr r1, =CCCR
str r2, [r1]
@@ -215,7 +215,7 @@ mem_init:
/* Turn on needed clocks */
ldr r1, =CKEN
- ldr r2, =CFG_CKEN_VAL
+ ldr r2, =CONFIG_SYS_CKEN_VAL
str r2, [r1]
mov pc, r10
diff --git a/board/xsengine/u-boot.lds b/board/xsengine/u-boot.lds
index bf42e9f..1e88820 100644
--- a/board/xsengine/u-boot.lds
+++ b/board/xsengine/u-boot.lds
@@ -51,6 +51,6 @@ SECTIONS
. = ALIGN(4);
__bss_start = .;
- .bss (NOLOAD) : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}
generated by cgit v1.1 at 2024-12-13 09:17:01 +0000