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-rw-r--r--board/xaeniax/flash.c22
-rw-r--r--board/xaeniax/lowlevel_init.S66
-rw-r--r--board/xaeniax/u-boot.lds2
3 files changed, 45 insertions, 45 deletions
diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c
index 9874a14..b051c89 100644
--- a/board/xaeniax/flash.c
+++ b/board/xaeniax/flash.c
@@ -28,7 +28,7 @@
#include <linux/byteorder/swab.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#define FLASH_PORT_WIDTH32
@@ -65,7 +65,7 @@ unsigned long flash_init (void)
int i;
ulong size = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -85,13 +85,13 @@ unsigned long flash_init (void)
/* Protect monitor and environment sectors
*/
flash_protect ( FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0] );
flash_protect ( FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
return size;
}
@@ -203,10 +203,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
break;
}
- if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CFG_MAX_FLASH_SECT);
- info->sector_count = CFG_MAX_FLASH_SECT;
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
@@ -276,7 +276,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -410,7 +410,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data)
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S
index fe3e712..57e1620 100644
--- a/board/xaeniax/lowlevel_init.S
+++ b/board/xaeniax/lowlevel_init.S
@@ -29,7 +29,7 @@
#include <version.h>
#include <asm/arch/pxa-regs.h>
-DRAM_SIZE: .long CFG_DRAM_SIZE
+DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
@@ -47,67 +47,67 @@ lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
ldr r0,=GPSR0
- ldr r1,=CFG_GPSR0_VAL
+ ldr r1,=CONFIG_SYS_GPSR0_VAL
str r1,[r0]
ldr r0,=GPSR1
- ldr r1,=CFG_GPSR1_VAL
+ ldr r1,=CONFIG_SYS_GPSR1_VAL
str r1,[r0]
ldr r0,=GPSR2
- ldr r1,=CFG_GPSR2_VAL
+ ldr r1,=CONFIG_SYS_GPSR2_VAL
str r1,[r0]
ldr r0,=GPCR0
- ldr r1,=CFG_GPCR0_VAL
+ ldr r1,=CONFIG_SYS_GPCR0_VAL
str r1,[r0]
ldr r0,=GPCR1
- ldr r1,=CFG_GPCR1_VAL
+ ldr r1,=CONFIG_SYS_GPCR1_VAL
str r1,[r0]
ldr r0,=GPCR2
- ldr r1,=CFG_GPCR2_VAL
+ ldr r1,=CONFIG_SYS_GPCR2_VAL
str r1,[r0]
ldr r0,=GPDR0
- ldr r1,=CFG_GPDR0_VAL
+ ldr r1,=CONFIG_SYS_GPDR0_VAL
str r1,[r0]
ldr r0,=GPDR1
- ldr r1,=CFG_GPDR1_VAL
+ ldr r1,=CONFIG_SYS_GPDR1_VAL
str r1,[r0]
ldr r0,=GPDR2
- ldr r1,=CFG_GPDR2_VAL
+ ldr r1,=CONFIG_SYS_GPDR2_VAL
str r1,[r0]
ldr r0,=GAFR0_L
- ldr r1,=CFG_GAFR0_L_VAL
+ ldr r1,=CONFIG_SYS_GAFR0_L_VAL
str r1,[r0]
ldr r0,=GAFR0_U
- ldr r1,=CFG_GAFR0_U_VAL
+ ldr r1,=CONFIG_SYS_GAFR0_U_VAL
str r1,[r0]
ldr r0,=GAFR1_L
- ldr r1,=CFG_GAFR1_L_VAL
+ ldr r1,=CONFIG_SYS_GAFR1_L_VAL
str r1,[r0]
ldr r0,=GAFR1_U
- ldr r1,=CFG_GAFR1_U_VAL
+ ldr r1,=CONFIG_SYS_GAFR1_U_VAL
str r1,[r0]
ldr r0,=GAFR2_L
- ldr r1,=CFG_GAFR2_L_VAL
+ ldr r1,=CONFIG_SYS_GAFR2_L_VAL
str r1,[r0]
ldr r0,=GAFR2_U
- ldr r1,=CFG_GAFR2_U_VAL
+ ldr r1,=CONFIG_SYS_GAFR2_U_VAL
str r1,[r0]
ldr r0,=PSSR /* enable GPIO pins */
- ldr r1,=CFG_PSSR_VAL
+ ldr r1,=CONFIG_SYS_PSSR_VAL
str r1,[r0]
/* ---------------------------------------------------------------- */
@@ -145,17 +145,17 @@ mem_init:
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
- ldr r2,=CFG_MSC0_VAL
+ ldr r2,=CONFIG_SYS_MSC0_VAL
str r2,[r1, #MSC0_OFFSET]
ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
/* MSC1: nCS(2,3) */
- ldr r2,=CFG_MSC1_VAL
+ ldr r2,=CONFIG_SYS_MSC1_VAL
str r2,[r1, #MSC1_OFFSET]
ldr r2,[r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
- ldr r2,=CFG_MSC2_VAL
+ ldr r2,=CONFIG_SYS_MSC2_VAL
str r2,[r1, #MSC2_OFFSET]
ldr r2,[r1, #MSC2_OFFSET]
@@ -164,37 +164,37 @@ mem_init:
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
- ldr r2,=CFG_MECR_VAL
+ ldr r2,=CONFIG_SYS_MECR_VAL
str r2,[r1, #MECR_OFFSET]
ldr r2,[r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
- ldr r2,=CFG_MCMEM0_VAL
+ ldr r2,=CONFIG_SYS_MCMEM0_VAL
str r2,[r1, #MCMEM0_OFFSET]
ldr r2,[r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
- ldr r2,=CFG_MCMEM1_VAL
+ ldr r2,=CONFIG_SYS_MCMEM1_VAL
str r2,[r1, #MCMEM1_OFFSET]
ldr r2,[r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2,=CFG_MCATT0_VAL
+ ldr r2,=CONFIG_SYS_MCATT0_VAL
str r2,[r1, #MCATT0_OFFSET]
ldr r2,[r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2,=CFG_MCATT1_VAL
+ ldr r2,=CONFIG_SYS_MCATT1_VAL
str r2,[r1, #MCATT1_OFFSET]
ldr r2,[r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2,=CFG_MCIO0_VAL
+ ldr r2,=CONFIG_SYS_MCIO0_VAL
str r2,[r1, #MCIO0_OFFSET]
ldr r2,[r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2,=CFG_MCIO1_VAL
+ ldr r2,=CONFIG_SYS_MCIO1_VAL
str r2,[r1, #MCIO1_OFFSET]
ldr r2,[r1, #MCIO1_OFFSET]
@@ -207,7 +207,7 @@ mem_init:
/* ---------------------------------------------------------------- */
@ get the mdrefr settings
- ldr r4,=CFG_MDREFR_VAL
+ ldr r4,=CONFIG_SYS_MDREFR_VAL
@ write back mdrefr
str r4,[r1, #MDREFR_OFFSET]
@@ -261,7 +261,7 @@ mem_init:
/* Step 4d: */
/* fetch platform value of mdcnfg */
@
- ldr r2, =CFG_MDCNFG_VAL
+ ldr r2, =CONFIG_SYS_MDCNFG_VAL
@ disable all sdram banks
@
@@ -296,7 +296,7 @@ mem_init:
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
- ldr r3, =CFG_DRAM_BASE
+ ldr r3, =CONFIG_SYS_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
@@ -326,7 +326,7 @@ mem_init:
/* Step 4h: Write MDMRS. */
- ldr r2, =CFG_MDMRS_VAL
+ ldr r2, =CONFIG_SYS_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
@@ -342,7 +342,7 @@ initirqs:
ldr r2, =ICLR
str r1, [r2]
- ldr r1, =CFG_ICMR_VAL /* mask all interrupts at the controller */
+ ldr r1, =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
ldr r2, =ICMR
str r1, [r2]
@@ -388,7 +388,7 @@ initclks:
@
test:
ldr r1, =CKEN
- ldr r2, =CFG_CKEN_VAL
+ ldr r2, =CONFIG_SYS_CKEN_VAL
str r2, [r1]
/* ---------------------------------------------------------------- */
diff --git a/board/xaeniax/u-boot.lds b/board/xaeniax/u-boot.lds
index 14d264a..7cf9fdf 100644
--- a/board/xaeniax/u-boot.lds
+++ b/board/xaeniax/u-boot.lds
@@ -51,6 +51,6 @@ SECTIONS
. = ALIGN(4);
__bss_start = .;
- .bss (NOLOAD) : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}
generated by cgit v1.1 at 2024-11-18 22:51:28 +0000