diff options
Diffstat (limited to 'board/w7o')
| -rw-r--r-- | board/w7o/fpga.c | 32 | ||||
| -rw-r--r-- | board/w7o/w7o.c | 16 | ||||
| -rw-r--r-- | board/w7o/w7o.h | 12 |
3 files changed, 30 insertions, 30 deletions
diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c index 97af924..336bfba 100644 --- a/board/w7o/fpga.c +++ b/board/w7o/fpga.c @@ -77,17 +77,17 @@ fpgaDownload(unsigned char *saddr, dest = (unsigned short *)daddr; /* Get DCR output register */ - grego = in32(IBM405GP_GPIO0_OR); + grego = in32(PPC405GP_GPIO0_OR); /* Reset FPGA */ grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(IBM405GP_GPIO0_OR, grego); + out32(PPC405GP_GPIO0_OR, grego); /* Setup timeout timer */ start = get_timer(0); /* Wait for FPGA init line */ - while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */ + while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */ /* Check for timeout - 100us max, so use 3ms */ if (get_timer(start) > 3) { printf(" failed to start init.\n"); @@ -100,10 +100,10 @@ fpgaDownload(unsigned char *saddr, /* Unreset FPGA */ grego |= GPIO_XCV_PROG; /* PROG line high */ - out32(IBM405GP_GPIO0_OR, grego); + out32(PPC405GP_GPIO0_OR, grego); /* Wait for FPGA end of init period . */ - while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */ + while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */ /* Check for timeout */ if (get_timer(start) > 3) { @@ -112,7 +112,7 @@ fpgaDownload(unsigned char *saddr, /* Reset FPGA */ grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(IBM405GP_GPIO0_OR, grego); + out32(PPC405GP_GPIO0_OR, grego); goto done; } @@ -127,18 +127,18 @@ fpgaDownload(unsigned char *saddr, mtdcr(CPC0_CR0, greg); /* ... just do it */ /* turn on open drain for CNFG */ - greg = in32(IBM405GP_GPIO0_ODR); /* get open drain register */ + greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */ greg |= cnfg; /* CNFG open drain */ - out32(IBM405GP_GPIO0_ODR, greg); /* .. just do it */ + out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */ /* Turn output enable on for CNFG */ - greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */ + greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ greg |= cnfg; /* CNFG tristate inactive */ - out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */ + out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ /* Setup FPGA for programming */ grego &= ~cnfg; /* CONFIG line low */ - out32(IBM405GP_GPIO0_OR, grego); + out32(PPC405GP_GPIO0_OR, grego); /* * Program the FPGA @@ -149,12 +149,12 @@ fpgaDownload(unsigned char *saddr, /* Done programming */ grego |= cnfg; /* CONFIG line high */ - out32(IBM405GP_GPIO0_OR, grego); + out32(PPC405GP_GPIO0_OR, grego); /* Turn output enable OFF for CNFG */ - greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */ + greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ greg &= ~cnfg; /* CNFG tristate inactive */ - out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */ + out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ /* Toggle IRQ/GPIO */ greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ @@ -180,7 +180,7 @@ fpgaDownload(unsigned char *saddr, start = get_timer(0); /* Wait for FPGA end of programming period . */ - while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */ + while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */ /* Check for timeout */ if (get_timer(start) > 3) { @@ -189,7 +189,7 @@ fpgaDownload(unsigned char *saddr, /* Reset FPGA */ grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(IBM405GP_GPIO0_OR, grego); + out32(PPC405GP_GPIO0_OR, grego); goto done; } diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 1e3ceb2..daf7f53 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -47,9 +47,9 @@ int board_early_init_f (void) /* * Setup GPIO pins - reset devices. */ - out32 (IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ - out32 (IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ - out32 (IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ + out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ + out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ + out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -78,9 +78,9 @@ int board_early_init_f (void) /* * Setup GPIO pins */ - out32 (IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ - out32 (IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ - out32 (IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ + out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ + out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ + out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -238,14 +238,14 @@ int misc_init_r (void) #if defined(CONFIG_W7OLMG) unsigned long greg; /* GPIO Register */ - greg = in32 (IBM405GP_GPIO0_OR); + greg = in32 (PPC405GP_GPIO0_OR); /* * XXX - Unreset devices - this should be moved into VxWorks driver code */ greg |= 0x41800000L; /* SAM, PHY, Galileo */ - out32 (IBM405GP_GPIO0_OR, greg); /* set output pins to default */ + out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */ #endif /* CONFIG_W7OLMG */ /* diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h index 8458166..d6f50e2 100644 --- a/board/w7o/w7o.h +++ b/board/w7o/w7o.h @@ -25,13 +25,13 @@ #define _W7O_H_ #include <config.h> -/* IBM 405GP PowerPC GPIO registers */ -#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */ -#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */ -#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */ -#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */ +/* AMCC 405GP PowerPC GPIO registers */ +#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */ +#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */ +#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */ +#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */ -/* IBM 405GP DCRs */ +/* AMCC 405GP DCRs */ #define CPC0_CR0 0xb1 /* Chip control register 0 */ /* LMG FPGA <=> CPU GPIO signals */ |