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-rw-r--r--board/v38b/ethaddr.c91
-rw-r--r--board/v38b/u-boot.lds3
-rw-r--r--board/v38b/v38b.c104
3 files changed, 84 insertions, 114 deletions
diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c
index aaa629e..4e2494e 100644
--- a/board/v38b/ethaddr.c
+++ b/board/v38b/ethaddr.c
@@ -1,5 +1,4 @@
/*
- *
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -25,48 +24,13 @@
#include <common.h>
#include <mpc5xxx.h>
-#define GPIO_ENABLE (MPC5XXX_WU_GPIO)
-
-/* Open Drain Emulation Register */
-#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04)
-
-/* Data Direction Register */
-#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08)
-
-/* Data Value Out Register */
-#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C)
-
-/* Interrupt Enable Register */
-#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10)
-
-/* Individual Interrupt Enable Register */
-#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14)
-
-/* Interrupt Type Register */
-#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18)
-
-/* Master Enable Register */
-#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C)
-
-/* Data Input Value Register */
-#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20)
-
-/* Status Register */
-#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24)
-
-#define PSC6_0 0x10000000
-#define WKUP_7 0x80000000
-
-/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */
-#define GPIO_PIN PSC6_0
+/* For the V38B board the pin is GPIO_PSC_6 */
+#define GPIO_PIN GPIO_PSC6_0
#define NO_ERROR 0
#define ERR_NO_NUMBER 1
#define ERR_BAD_NUMBER 2
-typedef volatile unsigned long GPIO_REG;
-typedef GPIO_REG *GPIO_REG_PTR;
-
static int is_high(void);
static int check_device(void);
static void io_out(int value);
@@ -79,33 +43,34 @@ static void write_byte(unsigned char command);
void read_2501_memory(unsigned char *psernum, unsigned char *perr);
void board_get_enetaddr(uchar *enetaddr);
+
static int is_high()
{
- return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN);
+ return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
}
static void io_out(int value)
{
if (value)
- *((vu_long *) GPIO_DVOR) |= GPIO_PIN;
+ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
else
- *((vu_long *) GPIO_DVOR) &= ~GPIO_PIN;
+ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
}
static void io_input()
{
- *((vu_long *) GPIO_DDR) &= ~GPIO_PIN;
+ *((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
udelay(3); /* allow input to settle */
}
static void io_output()
{
- *((vu_long *) GPIO_DDR) |= GPIO_PIN;
+ *((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
}
static void init_gpio()
{
- *((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */
+ *((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */
}
void read_2501_memory(unsigned char *psernum, unsigned char *perr)
@@ -117,8 +82,8 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr)
*perr = 0;
crcval = 0;
- for (i=0; i<NBYTES; i++)
-
+ for (i = 0; i < NBYTES; i++)
+ buf[i] = 0;
if (!check_device())
*perr = ERR_NO_NUMBER;
@@ -130,10 +95,10 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr)
write_byte(0x00);
read_byte(&crcval); /* Read CRC of address and command */
- for (i=0; i<NBYTES; i++)
- read_byte( &buf[i] );
+ for (i = 0; i < NBYTES; i++)
+ read_byte(&buf[i]);
}
- if (strncmp((const char*) &buf[11], "MAREL IEEE 802.3", 16)) {
+ if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
*perr = ERR_BAD_NUMBER;
psernum[0] = 0x00;
psernum[1] = 0xE0;
@@ -141,8 +106,7 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr)
psernum[3] = 0xFF;
psernum[4] = 0xFF;
psernum[5] = 0xFF;
- }
- else {
+ } else {
psernum[0] = 0x00;
psernum[1] = 0xE0;
psernum[2] = 0xEE;
@@ -173,27 +137,23 @@ static void write_byte(unsigned char command)
{
char i;
- for (i=0; i<8; i++) {
+ for (i = 0; i < 8; i++) {
/* 1 us to 15 us low pulse starts bit slot */
/* Start with high pulse for 3 us */
io_input();
-
udelay(3);
io_out(0);
io_output();
-
udelay(3);
if (command & 0x01) {
/* 60 us high for 1-bit */
io_input();
udelay(60);
- }
- else {
+ } else
/* 60 us low for 0-bit */
udelay(60);
- }
/* Leave pin as input */
io_input();
@@ -201,11 +161,11 @@ static void write_byte(unsigned char command)
}
}
-static void read_byte(unsigned char *data)
+static void read_byte(unsigned char *data)
{
unsigned char i, rdat = 0;
- for (i=0; i<8; i++) {
+ for (i = 0; i < 8; i++) {
/* read one bit from one-wire device */
/* 1 - 15 us low starts bit slot */
@@ -233,22 +193,21 @@ static void read_byte(unsigned char *data)
void board_get_enetaddr(uchar *enetaddr)
{
- unsigned char sn[6], err=NO_ERROR;
+ unsigned char sn[6], err = NO_ERROR;
init_gpio();
read_2501_memory(sn, &err);
if (err == NO_ERROR) {
- sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
+ sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
printf("MAC address: %s\n", enetaddr);
- setenv("ethaddr", enetaddr);
- }
- else {
- sprintf(enetaddr, "00:01:02:03:04:05");
+ setenv("ethaddr", (char *)enetaddr);
+ } else {
+ sprintf((char *)enetaddr, "00:01:02:03:04:05");
printf("Error reading MAC address.\n");
printf("Setting default to %s\n", enetaddr);
- setenv("ethaddr", enetaddr);
+ setenv("ethaddr", (char *)enetaddr);
}
}
diff --git a/board/v38b/u-boot.lds b/board/v38b/u-boot.lds
index 6ec5256..4fdea6b 100644
--- a/board/v38b/u-boot.lds
+++ b/board/v38b/u-boot.lds
@@ -61,6 +61,7 @@ SECTIONS
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
@@ -93,11 +94,13 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
index 99fe7db..dede996 100644
--- a/board/v38b/v38b.c
+++ b/board/v38b/v38b.c
@@ -28,43 +28,44 @@
#include <mpc5xxx.h>
#include <asm/processor.h>
+
#ifndef CFG_RAMBOOT
static void sdram_start(int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif /* SDRAM_DDR */
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif /* !CFG_RAMBOOT */
@@ -80,18 +81,18 @@ long int initdram(int board_type)
ulong test1, test2;
/* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
__asm__ volatile ("sync");
/* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif /* SDRAM_DDR */
@@ -112,20 +113,20 @@ long int initdram(int board_type)
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0)
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
else
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
/* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
- test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
- test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
@@ -139,22 +140,22 @@ long int initdram(int board_type)
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0)
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
else
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13)
dramsize = (1 << (dramsize - 0x13)) << 20;
else
dramsize = 0;
/* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13)
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
else
@@ -176,7 +177,7 @@ long int initdram(int board_type)
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
__asm__ volatile ("sync");
}
@@ -194,27 +195,42 @@ int checkboard (void)
int board_early_init_r(void)
{
/*
- * Now, when we are in RAM, enable flash write access for detection process.
- * Note that CS_BOOT cannot be cleared when executing in flash.
+ * Now, when we are in RAM, enable flash write access for the
+ * detection process. Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+#ifdef CONFIG_HW_WATCHDOG
+ /*
+ * Enable and configure the direction (output) of PSC3_9 - watchdog
+ * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
+ * Manual.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
+#endif /* CONFIG_HW_WATCHDOG */
+
+ /*
+ * Enable GPIO_WKUP_7 to "read the status of the actual power
+ * situation". Default direction is input, so no need to set it
+ * explicitly.
*/
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
return 0;
}
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-
-#define GPIO_PSC1_4 0x01000000UL
-
void init_ide_reset(void)
{
debug("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
/* Deassert reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
@@ -223,30 +239,22 @@ void ide_set_reset(int idereset)
debug("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
/* Make a delay. MPC5200 spec says 25 usec min */
udelay(500000);
} else
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
-void led_d4_on(void)
-{
- /* TIMER7 as GPIO output low */
- *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24;
-}
-
-
-void led_d4_off(void)
-{
- /* TIMER7 as GPIO output high */
- *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34;
-}
-
-
+#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
-/* TODO fill this in */
+ /*
+ * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
+ * we need a positive or negative transition on WDI i.e., our PSC3_9.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
}
+#endif /* CONFIG_HW_WATCHDOG */
generated by cgit v1.1 at 2024-12-14 22:31:40 +0000