diff options
Diffstat (limited to 'board/trizepsiv')
| -rw-r--r-- | board/trizepsiv/lowlevel_init.S | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S index d886938..128d554 100644 --- a/board/trizepsiv/lowlevel_init.S +++ b/board/trizepsiv/lowlevel_init.S @@ -49,119 +49,119 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPSR3 - ldr r1, =CFG_GPSR3_VAL + ldr r1, =CONFIG_SYS_GPSR3_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPCR3 - ldr r1, =CFG_GPCR3_VAL + ldr r1, =CONFIG_SYS_GPCR3_VAL str r1, [r0] ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL + ldr r1, =CONFIG_SYS_GRER0_VAL str r1, [r0] ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL + ldr r1, =CONFIG_SYS_GRER1_VAL str r1, [r0] ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL + ldr r1, =CONFIG_SYS_GRER2_VAL str r1, [r0] ldr r0, =GRER3 - ldr r1, =CFG_GRER3_VAL + ldr r1, =CONFIG_SYS_GRER3_VAL str r1, [r0] ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL + ldr r1, =CONFIG_SYS_GFER0_VAL str r1, [r0] ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL + ldr r1, =CONFIG_SYS_GFER1_VAL str r1, [r0] ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL + ldr r1, =CONFIG_SYS_GFER2_VAL str r1, [r0] ldr r0, =GFER3 - ldr r1, =CFG_GFER3_VAL + ldr r1, =CONFIG_SYS_GFER3_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GPDR3 - ldr r1, =CFG_GPDR3_VAL + ldr r1, =CONFIG_SYS_GPDR3_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =GAFR3_L - ldr r1, =CFG_GAFR3_L_VAL + ldr r1, =CONFIG_SYS_GAFR3_L_VAL str r1, [r0] ldr r0, =GAFR3_U - ldr r1, =CFG_GAFR3_U_VAL + ldr r1, =CONFIG_SYS_GAFR3_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ---------------------------------------------------------------- */ @@ -199,17 +199,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -218,44 +218,44 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] /* ---------------------------------------------------------------- */ /* Step 2c: Write FLYCNFG FIXME: what's that??? */ /* ---------------------------------------------------------------- */ - ldr r2, =CFG_FLYCNFG_VAL + ldr r2, =CONFIG_SYS_FLYCNFG_VAL str r2, [r1, #FLYCNFG_OFFSET] str r2, [r1, #FLYCNFG_OFFSET] @@ -270,7 +270,7 @@ mem_init: ldr r2, =0xFFF bic r4, r4, r2 - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL and r3, r3, r2 orr r4, r4, r3 @@ -300,7 +300,7 @@ mem_init: /* synchronous static memory. Note that SXLCR need not be written */ /* at this time. */ - ldr r2, =CFG_SXCNFG_VAL + ldr r2, =CONFIG_SYS_SXCNFG_VAL str r2, [r1, #SXCNFG_OFFSET] /* ---------------------------------------------------------------- */ @@ -329,7 +329,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) @@ -357,7 +357,7 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -379,7 +379,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] /* enable APD */ @@ -443,11 +443,11 @@ initclks: /* Turn Off on-chip peripheral clocks (except for memory) */ /* for re-configuration. */ ldr r1, =CKEN - ldr r2, =CFG_CKEN + ldr r2, =CONFIG_SYS_CKEN str r2, [r1] /* ... and write the core clock config register */ - ldr r2, =CFG_CCCR + ldr r2, =CONFIG_SYS_CCCR ldr r1, =CCCR str r2, [r1] |