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-rw-r--r--board/tqm834x/config.mk1
-rw-r--r--board/tqm834x/pci.c36
-rw-r--r--board/tqm834x/tqm834x.c16
3 files changed, 26 insertions, 27 deletions
diff --git a/board/tqm834x/config.mk b/board/tqm834x/config.mk
index 9295e77..f172c4e 100644
--- a/board/tqm834x/config.mk
+++ b/board/tqm834x/config.mk
@@ -21,4 +21,3 @@
#
TEXT_BASE = 0x80000000
-
diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
index 590987c..5a23e6c 100644
--- a/board/tqm834x/pci.c
+++ b/board/tqm834x/pci.c
@@ -86,29 +86,29 @@ pci_init_board(void)
pci_conf = immr->pci_conf;
hose = &pci1_hose;
-
+
/*
- * Configure PCI controller and PCI_CLK_OUTPUT
+ * Configure PCI controller and PCI_CLK_OUTPUT
*/
/*
* WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
* line actually used for clocking all external PCI devices in TQM83xx.
- * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
+ * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
* unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
- * are known to hang the board; this issue is under investigation
+ * are known to hang the board; this issue is under investigation
* (13 oct 05)
*/
reg32 = OCCR_PCICOE1;
-#if 0
+#if 0
/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
reg32 = 0xff000000;
-#endif
+#endif
if (clk->spmr & SPMR_CKID) {
/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
* fields accordingly */
reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
-
+
reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
| OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
| OCCR_PCICD6 | OCCR_PCICD7);
@@ -138,7 +138,7 @@ pci_init_board(void)
* Configure PCI Outbound Translation Windows
*/
- /* PCI1 mem space */
+ /* PCI1 mem space */
pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
@@ -152,8 +152,8 @@ pci_init_board(void)
* Configure PCI Inbound Translation Windows
*/
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
pci_ctrl[0].pitar1 = 0x0;
pci_ctrl[0].pibar1 = 0x0;
pci_ctrl[0].piebar1 = 0x0;
@@ -179,10 +179,10 @@ pci_init_board(void)
/* System memory space */
pci_set_region(hose->regions + 2,
CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
+ CONFIG_PCI_SYS_MEM_PHYS,
+ CONFIG_PCI_SYS_MEM_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
hose->region_count = 3;
pci_setup_indirect(hose,
@@ -195,18 +195,18 @@ pci_init_board(void)
* Write to Command register
*/
reg16 = 0xff;
- pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
+ pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
&reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
+ pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
reg16);
/*
* Clear non-reserved bits in status register.
*/
- pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
+ pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
0xffff);
- pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
+ pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
0x80);
#ifdef CONFIG_PCI_SCAN_SHOW
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index f681dc8..dada673 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -77,7 +77,7 @@ int board_early_init_r (void) {
/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return 0;
-
+
/* detect the number of Flash banks */
return detect_num_flash_banks();
}
@@ -108,7 +108,7 @@ long int initdram (int board_type)
set_ddr_config();
udelay(200);
-
+
/* enable DDR controller */
im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
SDRAM_CFG_SREN |
@@ -154,7 +154,7 @@ int checkboard (void)
/* get bus width */
w = 32;
- if (immr->reset.rcwh & RCWH_PCI64)
+ if (immr->reset.rcwh & RCWH_PCI64)
w = 64;
/* get clock */
@@ -192,7 +192,7 @@ static int detect_num_flash_banks(void)
ulong total_size;
tqm834x_num_flash_banks = 2; /* assume two banks */
-
+
/* Get bank 1 and 2 information */
bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
debug("Bank1 size: %lu\n", bank1_size);
@@ -318,10 +318,10 @@ static long int get_ddr_bank_size(short cs, volatile long *base)
set_cs_config(cs, 0);
return 0;
}
-
+
debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
-
+
/* configure cs ro detected params */
set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
conf[detected].col);
@@ -367,7 +367,7 @@ static void set_ddr_config(void) {
im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
SYNC;
-
+
/* timing configuration */
im->ddr.timing_cfg_1 =
(4 << TIMING_CFG1_PRETOACT_SHIFT) |
@@ -389,7 +389,7 @@ static void set_ddr_config(void) {
SDRAM_CFG_SREN |
SDRAM_CFG_SDRAM_TYPE_DDR;
SYNC;
-
+
/* Set SDRAM mode */
im->ddr.sdram_mode =
((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<