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-rw-r--r--board/toradex/colibri_t20/Kconfig12
-rw-r--r--board/toradex/colibri_t20/MAINTAINERS7
-rw-r--r--board/toradex/colibri_t20/Makefile9
-rw-r--r--board/toradex/colibri_t20/colibri_t20.c65
4 files changed, 93 insertions, 0 deletions
diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig
new file mode 100644
index 0000000..7f373b2
--- /dev/null
+++ b/board/toradex/colibri_t20/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_COLIBRI_T20
+
+config SYS_BOARD
+ default "colibri_t20"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "colibri_t20"
+
+endif
diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS
new file mode 100644
index 0000000..b251c00
--- /dev/null
+++ b/board/toradex/colibri_t20/MAINTAINERS
@@ -0,0 +1,7 @@
+COLIBRI_T20
+M: Lucas Stach <dev@lynxeye.de>
+S: Maintained
+F: board/toradex/colibri_t20/
+F: include/configs/colibri_t20.h
+F: configs/colibri_t20_defconfig
+F: arch/arm/dts/tegra20-colibri.dtb
diff --git a/board/toradex/colibri_t20/Makefile b/board/toradex/colibri_t20/Makefile
new file mode 100644
index 0000000..86f78d9
--- /dev/null
+++ b/board/toradex/colibri_t20/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2012 Lucas Stach
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y += colibri_t20.o
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
new file mode 100644
index 0000000..8ae9ccf
--- /dev/null
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+ pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+
+ /*
+ * configure pingroup ATC to something unrelated to
+ * avoid ATC overriding KBC
+ */
+ pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+ /* module internal USB bus to connect ethernet chipset */
+ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+
+ /* ULPI reference clock output */
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+
+ /* PHY reset GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
+
+ /* VBus GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_DTE);
+
+ /* Reset ASIX using LAN_RESET */
+ gpio_request(GPIO_PV4, "LAN_RESET");
+ gpio_direction_output(GPIO_PV4, 0);
+ pinmux_tristate_disable(PMUX_PINGRP_GPV);
+ udelay(5);
+ gpio_set_value(GPIO_PV4, 1);
+
+ /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
+ pinmux_tristate_disable(PMUX_PINGRP_SPIG);
+}
+#endif