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-rw-r--r--board/ti/am3517crane/Makefile46
-rw-r--r--board/ti/am3517crane/am3517crane.c75
-rw-r--r--board/ti/am3517crane/am3517crane.h395
-rw-r--r--board/ti/am3517crane/config.mk29
-rw-r--r--board/ti/beagle/Makefile4
-rw-r--r--board/ti/beagle/beagle.c169
-rw-r--r--board/ti/beagle/beagle.h42
-rw-r--r--board/ti/beagle/led.c91
8 files changed, 830 insertions, 21 deletions
diff --git a/board/ti/am3517crane/Makefile b/board/ti/am3517crane/Makefile
new file mode 100644
index 0000000..1fe2bca
--- /dev/null
+++ b/board/ti/am3517crane/Makefile
@@ -0,0 +1,46 @@
+#
+# Author: Srinath R <srinath@mistralsolutions.com>
+#
+# Based on logicpd/am3517evm/Makefile
+#
+# Copyright (C) 2011 Mistral Solutions Pvt Ltd
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := am3517crane.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
new file mode 100644
index 0000000..d007044
--- /dev/null
+++ b/board/ti/am3517crane/am3517crane.c
@@ -0,0 +1,75 @@
+/*
+ * am3517crane.c - board file for AM3517 CraneBoard
+ *
+ * Author: Srinath.R <srinath@mistralsolutions.com>
+ *
+ * Based on logicpd/am3517evm/am3517evm.c
+ *
+ * Copyright (C) 2011 Mistral Solutions Pvt Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517crane.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_AM3517CRANE();
+}
diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h
new file mode 100644
index 0000000..41db972
--- /dev/null
+++ b/board/ti/am3517crane/am3517crane.h
@@ -0,0 +1,395 @@
+/*
+ * am3517crane.h - Header file for the AM3517 CraneBoard.
+ *
+ * Author: Srinath R <srinath@mistralsolutions.com>
+ *
+ * Based on logicpd/am3517evm/am3517evm.h
+ *
+ * Copyright (C) 2011 Mistral Solutions Pvt Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517CRANE_H_
+#define _AM3517CRANE_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CraneBoard",
+ "NAND",
+};
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
+#define CONTROL_PADCONF_CCDC_HD 0x01E8
+#define CONTROL_PADCONF_CCDC_VD 0x01EA
+#define CONTROL_PADCONF_CCDC_WEN 0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
+#define CONTROL_PADCONF_RMII_RXD0 0x0202
+#define CONTROL_PADCONF_RMII_RXD1 0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
+#define CONTROL_PADCONF_RMII_RXER 0x0208
+#define CONTROL_PADCONF_RMII_TXD0 0x020A
+#define CONTROL_PADCONF_RMII_TXD1 0x020C
+#define CONTROL_PADCONF_RMII_TXEN 0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD 0x0214
+#define CONTROL_PADCONF_HECC1_RXD 0x0216
+#define CONTROL_PADCONF_SYS_BOOT7 0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
+#define CONTROL_PADCONF_SYS_BOOT8 0x0226
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517CRANE()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (M0))\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (M0))\
+ MUX_VAL(CP(SDRC_CKE1), (M0))\
+ /*sdrc_strben_dly0*/\
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\
+ /*sdrc_strben_dly1*/\
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (M7))\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A6), (M7))\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A9), (M7))\
+ MUX_VAL(CP(GPMC_A10), (M7))\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_NCS2), (M7))\
+ MUX_VAL(CP(GPMC_NCS3), (M7))\
+ MUX_VAL(CP(GPMC_NCS4), (M7))\
+ MUX_VAL(CP(GPMC_NCS5), (M7))\
+ MUX_VAL(CP(GPMC_NCS6), (M7))\
+ MUX_VAL(CP(GPMC_NCS7), (M7))\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NBE1), (M7))\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT1), (M7))\
+ MUX_VAL(CP(GPMC_WAIT2), (M7))\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\
+ /*MMC1*/\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\
+ /*MMC2*/\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\
+ /*McBSP*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (M7))\
+ MUX_VAL(CP(MCBSP2_CLKX), (M7))\
+ MUX_VAL(CP(MCBSP2_DR), (M7))\
+ MUX_VAL(CP(MCBSP2_DX), (M7))\
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (M7))\
+ MUX_VAL(CP(MCBSP4_DR), (M7))\
+ MUX_VAL(CP(MCBSP4_DX), (M7))\
+ MUX_VAL(CP(MCBSP4_FSX), (M7))\
+ /*UART*/\
+ MUX_VAL(CP(UART1_TX), (M7))\
+ MUX_VAL(CP(UART1_RTS), (M7))\
+ MUX_VAL(CP(UART1_CTS), (M7))\
+ MUX_VAL(CP(UART1_RX), (M7))\
+ \
+ MUX_VAL(CP(UART2_CTS), (M7))\
+ MUX_VAL(CP(UART2_RTS), (M7))\
+ MUX_VAL(CP(UART2_TX), (M7))\
+ MUX_VAL(CP(UART2_RX), (M7))\
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\
+ /*I2C 1, 2, 3*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
+ /*McSPI*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (M7))\
+ MUX_VAL(CP(MCSPI2_SIMO), (M7))\
+ MUX_VAL(CP(MCSPI2_SOMI), (M7))\
+ MUX_VAL(CP(MCSPI2_CS0), (M7))\
+ MUX_VAL(CP(MCSPI2_CS1), (M7))\
+ /*CCDC*/\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\
+ /*RMII*/\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0))\
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_RXER), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0))\
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\
+ /*HECC*/\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\
+ /*HSUSB*/\
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\
+ /*HDQ*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\
+ /*Control and debug*/\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\
+ /*SYS_nRESWARM*/\
+ MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\
+ /*JTAG*/\
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\
+ /*ETK (ES2 onwards)*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D10_ES2), (M7))\
+ MUX_VAL(CP(ETK_D11_ES2), (M7))\
+ MUX_VAL(CP(ETK_D12_ES2), (M7))\
+ MUX_VAL(CP(ETK_D13_ES2), (M7))\
+ MUX_VAL(CP(ETK_D14_ES2), (M7))\
+ MUX_VAL(CP(ETK_D15_ES2), (M7))\
+ /*Die to Die*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\
+
+#endif /* _AM3517CRANE_H_ */
diff --git a/board/ti/am3517crane/config.mk b/board/ti/am3517crane/config.mk
new file mode 100644
index 0000000..c6a18b5
--- /dev/null
+++ b/board/ti/am3517crane/config.mk
@@ -0,0 +1,29 @@
+#
+# Author: Srinath R <srinath@mistralsolutions.com>
+#
+# Based on logicpd/am3517evm/config.mk
+#
+# Copyright (C) 2011 Mistral Solutions Pvt Ltd
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
index 3b4aaac..d9f445f 100644
--- a/board/ti/beagle/Makefile
+++ b/board/ti/beagle/Makefile
@@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := beagle.o
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_STATUS_LED) += led.o
+COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index c066d6e..4e194a2 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -30,6 +30,9 @@
* MA 02111-1307 USA
*/
#include <common.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
@@ -37,8 +40,19 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/gpio.h>
#include <asm/mach-types.h>
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include <asm/arch/ehci_omap3.h>
+/* from drivers/usb/host/ehci-core.h */
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+#endif
#include "beagle.h"
+#define pr_debug(fmt, args...) debug(fmt, ##args)
+
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 1
#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
@@ -48,7 +62,12 @@
#define TINCANTOOLS_TRAINER 0x04000100
#define TINCANTOOLS_SHOWDOG 0x03000100
#define KBADC_BEAGLEFPGA 0x01000600
-
+#define LW_BEAGLETOUCH 0x01000700
+#define BRAINMUX_LCDOG 0x01000800
+#define BRAINMUX_LCDOGTOUCH 0x02000800
+#define BBTOYS_WIFI 0x01000B00
+#define BBTOYS_VGA 0x02000B00
+#define BBTOYS_LCD 0x03000B00
#define BEAGLE_NO_EEPROM 0xffffffff
DECLARE_GLOBAL_DATA_PTR;
@@ -74,6 +93,10 @@ int board_init(void)
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
return 0;
}
@@ -148,23 +171,24 @@ int misc_init_r(void)
{
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+ struct control_prog_io *prog_io_base = (struct gpio *)OMAP34XX_CTRL_BASE;
+
+ /* Enable i2c2 pullup resisters */
+ writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
switch (get_board_revision()) {
case REVISION_AXBX:
printf("Beagle Rev Ax/Bx\n");
setenv("beaglerev", "AxBx");
- setenv("mpurate", "600");
break;
case REVISION_CX:
printf("Beagle Rev C1/C2/C3\n");
setenv("beaglerev", "Cx");
- setenv("mpurate", "600");
MUX_BEAGLE_C();
break;
case REVISION_C4:
printf("Beagle Rev C4\n");
setenv("beaglerev", "C4");
- setenv("mpurate", "720");
MUX_BEAGLE_C();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
@@ -172,10 +196,19 @@ int misc_init_r(void)
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
break;
- case REVISION_XM:
+ case REVISION_XM_A:
printf("Beagle xM Rev A\n");
setenv("beaglerev", "xMA");
- setenv("mpurate", "1000");
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ break;
+ case REVISION_XM_B:
+ printf("Beagle xM Rev B\n");
+ setenv("beaglerev", "xMB");
MUX_BEAGLE_XM();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
@@ -185,6 +218,12 @@ int misc_init_r(void)
break;
default:
printf("Beagle unknown 0x%02x\n", get_board_revision());
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
switch (get_expansion_id()) {
@@ -223,6 +262,29 @@ int misc_init_r(void)
MUX_KBADC_BEAGLEFPGA();
setenv("buddy", "beaglefpga");
break;
+ case LW_BEAGLETOUCH:
+ printf("Recognized Liquidware BeagleTouch board\n");
+ setenv("buddy", "beagletouch");
+ break;
+ case BRAINMUX_LCDOG:
+ printf("Recognized Brainmux LCDog board\n");
+ setenv("buddy", "lcdog");
+ break;
+ case BRAINMUX_LCDOGTOUCH:
+ printf("Recognized Brainmux LCDog Touch board\n");
+ setenv("buddy", "lcdogtouch");
+ break;
+ case BBTOYS_WIFI:
+ printf("Recognized BeagleBoardToys WiFi board\n");
+ MUX_BBTOYS_WIFI()
+ setenv("buddy", "bbtoys-wifi");
+ break;;
+ case BBTOYS_VGA:
+ printf("Recognized BeagleBoardToys VGA board\n");
+ break;;
+ case BBTOYS_LCD:
+ printf("Recognized BeagleBoardToys LCD board\n");
+ break;;
case BEAGLE_NO_EEPROM:
printf("No EEPROM on expansion board\n");
setenv("buddy", "none");
@@ -273,3 +335,98 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif
+
+#ifdef CONFIG_USB_EHCI
+
+#define GPIO_PHY_RESET 147
+
+/* Reset is needed otherwise the kernel-driver will throw an error. */
+int ehci_hcd_stop(void)
+{
+ pr_debug("Resetting OMAP3 EHCI\n");
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+ writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
+ return 0;
+}
+
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+ if(val == 15)
+ usb_stop();
+}
+
+/*
+ * Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
+ * See there for additional Copyrights.
+ */
+int ehci_hcd_init(void)
+{
+ pr_debug("Initializing OMAP3 ECHI\n");
+
+ /* Put the PHY in RESET */
+ omap_request_gpio(GPIO_PHY_RESET);
+ omap_set_gpio_direction(GPIO_PHY_RESET, 0);
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+
+ /* Hold the PHY in RESET for enough time till DIR is high */
+ /* Refer: ISSUE1 */
+ udelay(10);
+
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
+ sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
+ /*
+ * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
+ * and USBHOST_120M_FCLK (USBHOST_FCLK2)
+ */
+ sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
+ /* Enable USBTTL_ICLK */
+ sr32(&prcm_base->iclken3_core, 2, 1, 1);
+ /* Enable USBTTL_FCLK */
+ sr32(&prcm_base->fclken3_core, 2, 1, 1);
+ pr_debug("USB clocks enabled\n");
+
+ /* perform TLL soft reset, and wait until reset is complete */
+ writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+ /* Wait for TLL reset to complete */
+ while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
+ & OMAP_USBTLL_SYSSTATUS_RESETDONE));
+ pr_debug("TLL reset done\n");
+
+ writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
+ OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
+ OMAP_USBTLL_SYSCONFIG_CACTIVITY,
+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+
+ /* Put UHH in NoIdle/NoStandby mode */
+ writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
+ | OMAP_UHH_SYSCONFIG_SIDLEMODE
+ | OMAP_UHH_SYSCONFIG_CACTIVITY
+ | OMAP_UHH_SYSCONFIG_MIDLEMODE,
+ OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
+
+ /* setup burst configurations */
+ writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
+ OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
+
+ /*
+ * Refer ISSUE1:
+ * Hold the PHY in RESET for enough time till
+ * PHY is settled and ready
+ */
+ udelay(10);
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 1);
+
+ hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
+ hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
+
+ pr_debug("OMAP3 EHCI init done\n");
+ return 0;
+}
+
+#endif /* CONFIG_USB_EHCI */
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index b22b653..a7401b1 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -37,7 +37,8 @@ const omap3_sysinfo sysinfo = {
#define REVISION_AXBX 0x7
#define REVISION_CX 0x6
#define REVISION_C4 0x5
-#define REVISION_XM 0x0
+#define REVISION_XM_A 0x0
+#define REVISION_XM_B 0x1
/*
* IEN - Input Enable
@@ -273,18 +274,18 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
/* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\
/*Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
@@ -383,7 +384,8 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/
#define MUX_BEAGLE_XM() \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\
@@ -457,4 +459,16 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+#define MUX_BBTOYS_WIFI() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) /*GPIO_136 FM_EN/BT_WU*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 WLAN_IRQ*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/
+
#endif
diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c
new file mode 100644
index 0000000..df26552
--- /dev/null
+++ b/board/ti/beagle/led.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2010 Texas Instruments, Inc.
+ * Jason Kridner <jkridner@beagleboard.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+
+static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+
+/* GPIO pins for the LEDs */
+#define BEAGLE_LED_USR0 149
+#define BEAGLE_LED_USR1 150
+
+#ifdef STATUS_LED_GREEN
+void green_LED_off (void)
+{
+ __led_set (STATUS_LED_GREEN, 0);
+}
+
+void green_LED_on (void)
+{
+ __led_set (STATUS_LED_GREEN, 1);
+}
+#endif
+
+void __led_init (led_id_t mask, int state)
+{
+ __led_set (mask, state);
+}
+
+void __led_toggle (led_id_t mask)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask) {
+ if (STATUS_LED_ON == saved_state[0])
+ __led_set(STATUS_LED_BIT, 0);
+ else
+ __led_set(STATUS_LED_BIT, 1);
+ }
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask) {
+ if (STATUS_LED_ON == saved_state[1])
+ __led_set(STATUS_LED_BIT1, 0);
+ else
+ __led_set(STATUS_LED_BIT1, 1);
+ }
+#endif
+}
+
+void __led_set (led_id_t mask, int state)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask) {
+ if (!omap_request_gpio(BEAGLE_LED_USR0)) {
+ omap_set_gpio_direction(BEAGLE_LED_USR0, 0);
+ omap_set_gpio_dataout(BEAGLE_LED_USR0, state);
+ }
+ saved_state[0] = state;
+ }
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask) {
+ if (!omap_request_gpio(BEAGLE_LED_USR1)) {
+ omap_set_gpio_direction(BEAGLE_LED_USR1, 0);
+ omap_set_gpio_dataout(BEAGLE_LED_USR1, state);
+ }
+ saved_state[1] = state;
+ }
+#endif
+}
+
generated by cgit v1.1 at 2024-12-26 23:11:18 +0000