diff options
Diffstat (limited to 'board/ti/am43xx/board.c')
| -rw-r--r-- | board/ti/am43xx/board.c | 297 |
1 files changed, 283 insertions, 14 deletions
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index d744977..7e239f1 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -19,6 +19,7 @@ #include <asm/arch/gpio.h> #include <asm/emif.h> #include "board.h" +#include <power/tps65218.h> #include <miiphy.h> #include <cpsw.h> @@ -67,10 +68,13 @@ static int read_eeprom(struct am43xx_board_id *header) strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); am43xx_board_name[sizeof(header->name)] = 0; + strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); + am43xx_board_rev[sizeof(header->version)] = 0; + return 0; } -#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SKIP_LOWLEVEL_INIT #define NUM_OPPS 6 @@ -153,12 +157,16 @@ const struct emif_regs emif_regs_lpddr2 = { .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, .emif_ddr_phy_ctlr_1 = 0x0E084006, - .emif_rd_wr_exec_thresh = 0x00000405, + .emif_rd_wr_exec_thresh = 0x80000405, .emif_ddr_ext_phy_ctrl_1 = 0x04010040, .emif_ddr_ext_phy_ctrl_2 = 0x00500050, .emif_ddr_ext_phy_ctrl_3 = 0x00500050, .emif_ddr_ext_phy_ctrl_4 = 0x00500050, - .emif_ddr_ext_phy_ctrl_5 = 0x00500050 + .emif_ddr_ext_phy_ctrl_5 = 0x00500050, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF }; const u32 ext_phy_ctrl_const_base_lpddr2[] = { @@ -213,7 +221,83 @@ const struct emif_regs ddr3_emif_regs_400Mhz = { .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, - .emif_rd_wr_exec_thresh = 0x00000405 + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_beta = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000065, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_production = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { + .sdram_config = 0x638413b2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0e084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x80000000, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF }; const u32 ext_phy_ctrl_const_base_ddr3[] = { @@ -239,14 +323,111 @@ const u32 ext_phy_ctrl_const_base_ddr3[] = { 0x08102040 }; +const u32 ext_phy_ctrl_const_base_ddr3_beta[] = { + 0x00000000, + 0x00000045, + 0x00000046, + 0x00000048, + 0x00000047, + 0x00000000, + 0x0000004C, + 0x00000070, + 0x00000085, + 0x000000A3, + 0x00000000, + 0x0000000C, + 0x00000030, + 0x00000045, + 0x00000063, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +const u32 ext_phy_ctrl_const_base_ddr3_production[] = { + 0x00000000, + 0x00000044, + 0x00000044, + 0x00000046, + 0x00000046, + 0x00000000, + 0x00000059, + 0x00000077, + 0x00000093, + 0x000000A8, + 0x00000000, + 0x00000019, + 0x00000037, + 0x00000053, + 0x00000068, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = { + /* first 5 are taken care by emif_regs */ + 0x00700070, + + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0x00150015, + 0x00150015, + 0x00150015, + 0x00150015, + 0x00150015, + + 0x00800080, + 0x00800080, + + 0x40000000, + + 0x08102040, + + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } else if (board_is_evm_14_or_later()) { + *regs = ext_phy_ctrl_const_base_ddr3_production; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); + } else if (board_is_evm_12_or_later()) { + *regs = ext_phy_ctrl_const_base_ddr3_beta; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); + } else if (board_is_sk()) { + *regs = ext_phy_ctrl_const_base_ddr3_sk; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); } return; @@ -254,19 +435,12 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) const struct dpll_params *get_dpll_ddr_params(void) { - struct am43xx_board_id header; - - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (read_eeprom(&header) < 0) - puts("Could not get board ID.\n"); - if (board_is_eposevm()) return &epos_evm_dpll_ddr; - else if (board_is_gpevm()) + else if (board_is_gpevm() || board_is_sk()) return &gp_evm_dpll_ddr; - puts(" Board not supported\n"); + printf(" Board '%s' not supported\n", am43xx_board_name); return NULL; } @@ -302,7 +476,10 @@ static u32 get_sys_clk_index(void) static int get_opp_offset(int max_off, int min_off) { struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; - int opp = readl(&ctrl->dev_attr), offset, i; + int opp, offset, i; + + /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ + opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; for (i = max_off; i >= min_off; i--) { offset = opp & (1 << i); @@ -335,6 +512,46 @@ const struct dpll_params *get_dpll_per_params(void) return &dpll_per[ind]; } +void scale_vcores(void) +{ + const struct dpll_params *mpu_params; + int mpu_vdd; + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Get the frequency */ + mpu_params = get_dpll_mpu_params(); + + if (i2c_probe(TPS65218_CHIP_PM)) + return; + + if (mpu_params->m == 1000) { + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; + } else if (mpu_params->m == 600) { + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; + } else { + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set DCDC1 (CORE) voltage to 1.1V */ + if (tps65218_voltage_update(TPS65218_DCDC1, + TPS65218_DCDC_VOLT_SEL_1100MV)) { + puts("tps65218_voltage_update failure\n"); + return; + } + + /* Set DCDC2 (MPU) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { + puts("tps65218_voltage_update failure\n"); + return; + } +} + void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -369,18 +586,65 @@ void sdram_init(void) */ if (board_is_eposevm()) { config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_evm_14_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_production, 0); + } else if (board_is_evm_12_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_beta, 0); } else if (board_is_gpevm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); + } else if (board_is_sk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_sk_emif_regs_400Mhz, 0); } } #endif int board_init(void) { + struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; + u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, + modena_init0_bw_integer, modena_init0_watermark_0; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + /* Clear all important bits for DSS errata that may need to be tweaked*/ + mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & + MREQPRIO_0_SAB_INIT0_MASK; + + mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; + + modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & + BW_LIMITER_BW_FRAC_MASK; + + modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & + BW_LIMITER_BW_INT_MASK; + + modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & + BW_LIMITER_BW_WATERMARK_MASK; + + /* Setting MReq Priority of the DSS*/ + mreqprio_0 |= 0x77; + + /* + * Set L3 Fast Configuration Register + * Limiting bandwith for ARM core to 700 MBPS + */ + modena_init0_bw_fractional |= 0x10; + modena_init0_bw_integer |= 0x3; + + writel(mreqprio_0, &cdev->mreqprio_0); + writel(mreqprio_1, &cdev->mreqprio_1); + + writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); + writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); + writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); + return 0; } @@ -487,6 +751,11 @@ int board_eth_init(bd_t *bis) writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[0].phy_addr = 16; + } else if (board_is_sk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 4; + cpsw_slaves[1].phy_addr = 5; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |