diff options
Diffstat (limited to 'board/ti/am335x/board.c')
-rw-r--r-- | board/ti/am335x/board.c | 157 |
1 files changed, 150 insertions, 7 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 4330be6..56f4984 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -11,11 +11,13 @@ #include <common.h> #include <errno.h> #include <spl.h> +#include <serial.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/clk_synthesizer.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> @@ -37,7 +39,13 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO that controls power to DDR on EVM-SK */ -#define GPIO_DDR_VTT_EN 7 +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) +#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) +#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) +#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) +#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) +#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) +#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) #if defined(CONFIG_SPL_BUILD) || \ (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) @@ -52,6 +60,16 @@ static inline int __maybe_unused read_eeprom(void) return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); } +#ifndef CONFIG_DM_SERIAL +struct serial_device *default_serial_console(void) +{ + if (board_is_icev2()) + return &eserial4_device; + else + return &eserial1_device; +} +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, @@ -97,6 +115,13 @@ static const struct ddr_data ddr3_evm_data = { .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, }; +static const struct ddr_data ddr3_icev2_data = { + .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, + .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, +}; + static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, @@ -130,6 +155,17 @@ static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, }; +static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { + .cmd0csratio = MT41J128MJT125_RATIO_400MHz, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, + + .cmd1csratio = MT41J128MJT125_RATIO_400MHz, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, + + .cmd2csratio = MT41J128MJT125_RATIO_400MHz, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, +}; + static struct emif_regs ddr3_emif_reg_data = { .sdram_config = MT41J128MJT125_EMIF_SDCFG, .ref_ctrl = MT41J128MJT125_EMIF_SDREF, @@ -162,6 +198,17 @@ static struct emif_regs ddr3_evm_emif_reg_data = { PHY_EN_DYN_PWRDN, }; +static struct emif_regs ddr3_icev2_emif_reg_data = { + .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, + .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | + PHY_EN_DYN_PWRDN, +}; + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -339,7 +386,7 @@ const struct dpll_params *get_dpll_ddr_params(void) if (board_is_evm_sk()) return &dpll_ddr_evm_sk; - else if (board_is_bone_lt()) + else if (board_is_bone_lt() || board_is_icev2()) return &dpll_ddr_bone_black; else if (board_is_evm_15_or_later()) return &dpll_ddr_evm_sk; @@ -418,6 +465,11 @@ void sdram_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } + if (board_is_icev2()) { + gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); + } + if (board_is_evm_sk()) config_ddr(303, &ioregs_evmsk, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); @@ -429,12 +481,59 @@ void sdram_init(void) else if (board_is_evm_15_or_later()) config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); + else if (board_is_icev2()) + config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, + &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, + 0); else config_ddr(266, &ioregs, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); } #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void request_and_set_gpio(int gpio, char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret < 0) { + printf("%s: Unable to request %s\n", __func__, name); + return; + } + + ret = gpio_direction_output(gpio, 0); + if (ret < 0) { + printf("%s: Unable to set %s as output\n", __func__, name); + goto err_free_gpio; + } + + gpio_set_value(gpio, 1); + + return; + +err_free_gpio: + gpio_free(gpio); +} + +#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N); + +/** + * RMII mode on ICEv2 board needs 50MHz clock. Given the clock + * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle + * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to + * give 50MHz output for Eth0 and 1. + */ +static struct clk_synth cdce913_data = { + .id = 0x81, + .capacitor = 0x90, + .mux = 0x6d, + .pdiv2 = 0x2, + .pdiv3 = 0x2, +}; +#endif + /* * Basic board specific setup. Pinmux has been handled already. */ @@ -448,6 +547,23 @@ int board_init(void) #if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) + int rv; + + if (board_is_icev2()) { + REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); + REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); + + rv = setup_clock_synthesizer(&cdce913_data); + if (rv) { + printf("Clock synthesizer setup failed %d\n", rv); + return rv; + } + } +#endif + return 0; } @@ -515,6 +631,12 @@ static struct cpsw_platform_data cpsw_data = { }; #endif +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) + /* * This function will: * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr @@ -526,11 +648,6 @@ static struct cpsw_platform_data cpsw_data = { * Build in only these cases to avoid warnings about unused variables * when we build an SPL that has neither option but full U-Boot will. */ -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ - && defined(CONFIG_SPL_BUILD)) || \ - ((defined(CONFIG_DRIVER_TI_CPSW) || \ - defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; @@ -581,6 +698,12 @@ int board_eth_init(bd_t *bis) writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + } else if (board_is_icev2()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 1; + cpsw_slaves[1].phy_addr = 3; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = @@ -632,3 +755,23 @@ int board_eth_init(bd_t *bis) #endif #endif /* CONFIG_DM_ETH */ + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) + return 0; + else if (board_is_bone() && !strcmp(name, "am335x-bone")) + return 0; + else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) + return 0; + else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) + return 0; + else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) + return 0; + else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) + return 0; + else + return -1; +} +#endif |