summaryrefslogtreecommitdiff
path: root/board/sunxi/Kconfig
diff options
context:
space:
mode:
Diffstat (limited to 'board/sunxi/Kconfig')
-rw-r--r--board/sunxi/Kconfig290
1 files changed, 141 insertions, 149 deletions
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 6a4d764..4a21589 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -33,21 +33,103 @@ config MACH_SUN8I
endchoice
-if MACH_SUN6I || MACH_SUN8I
-
config DRAM_CLK
- int "sun6i dram clock speed"
- default 312
+ int "sunxi dram clock speed"
+ default 312 if MACH_SUN6I || MACH_SUN8I
+ default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
---help---
Set the dram clock speed, valid range 240 - 480, must be a multiple
of 24.
+if MACH_SUN5I || MACH_SUN7I
+config DRAM_MBUS_CLK
+ int "sunxi mbus clock speed"
+ default 300
+ ---help---
+ Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
+
+endif
+
config DRAM_ZQ
- int "sun6i dram zq value"
- default 123
+ int "sunxi dram zq value"
+ default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+ default 127 if MACH_SUN7I
---help---
Set the dram zq value.
+if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+config DRAM_EMR1
+ int "sunxi dram emr1 value"
+ default 0 if MACH_SUN4I
+ default 4 if MACH_SUN5I || MACH_SUN7I
+ ---help---
+ Set the dram controller emr1 value.
+
+config DRAM_ODT_EN
+ int "sunxi dram odt_en value"
+ default 0
+ ---help---
+ Set the dram controller odt_en parameter. This can be used to
+ enable/disable the ODT feature.
+
+config DRAM_TPR3
+ hex "sunxi dram tpr3 value"
+ default 0
+ ---help---
+ Set the dram controller tpr3 parameter. This parameter configures
+ the delay on the command lane and also phase shifts, which are
+ applied for sampling incoming read data. The default value 0
+ means that no phase/delay adjustments are necessary. Properly
+ configuring this parameter increases reliability at high DRAM
+ clock speeds.
+
+config DRAM_DQS_GATING_DELAY
+ hex "sunxi dram dqs_gating_delay value"
+ default 0
+ ---help---
+ Set the dram controller dqs_gating_delay parmeter. Each byte
+ encodes the DQS gating delay for each byte lane. The delay
+ granularity is 1/4 cycle. For example, the value 0x05060606
+ means that the delay is 5 quarter-cycles for one lane (1.25
+ cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
+ The default value 0 means autodetection. The results of hardware
+ autodetection are not very reliable and depend on the chip
+ temperature (sometimes producing different results on cold start
+ and warm reboot). But the accuracy of hardware autodetection
+ is usually good enough, unless running at really high DRAM
+ clocks speeds (up to 600MHz). If unsure, keep as 0.
+
+choice
+ prompt "sunxi dram timings"
+ default DRAM_TIMINGS_VENDOR_MAGIC
+ ---help---
+ Select the timings of the DDR3 chips.
+
+config DRAM_TIMINGS_VENDOR_MAGIC
+ bool "Magic vendor timings from Android"
+ ---help---
+ The same DRAM timings as in the Allwinner boot0 bootloader.
+
+config DRAM_TIMINGS_DDR3_1066F_1333H
+ bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
+ ---help---
+ Use the timings of the standard JEDEC DDR3-1066F speed bin for
+ DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
+ for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
+ used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
+ or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
+ that down binning to DDR3-1066F is supported (because DDR3-1066F
+ uses a bit faster timings than DDR3-1333H).
+
+config DRAM_TIMINGS_DDR3_800E_1066G_1333J
+ bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
+ ---help---
+ Use the timings of the slowest possible JEDEC speed bin for the
+ selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
+ DDR3-800E, DDR3-1066G or DDR3-1333J.
+
+endchoice
+
endif
config SYS_CONFIG_NAME
@@ -57,149 +139,6 @@ config SYS_CONFIG_NAME
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I
-choice
- prompt "Board"
-
-config TARGET_A10_OLINUXINO_L
- bool "A10_OLINUXINO_L"
- depends on MACH_SUN4I
-
-config TARGET_A10S_OLINUXINO_M
- bool "A10S_OLINUXINO_M"
- depends on MACH_SUN5I
-
-config TARGET_A13_OLINUXINOM
- bool "A13_OLINUXINOM"
- depends on MACH_SUN5I
-
-config TARGET_A13_OLINUXINO
- bool "A13_OLINUXINO"
- depends on MACH_SUN5I
-
-config TARGET_A20_OLINUXINO_L2
- bool "A20_OLINUXINO_L2"
- depends on MACH_SUN7I
-
-config TARGET_A20_OLINUXINO_L
- bool "A20_OLINUXINO_L"
- depends on MACH_SUN7I
-
-config TARGET_A20_OLINUXINO_M
- bool "A20_OLINUXINO_M"
- depends on MACH_SUN7I
-
-config TARGET_AUXTEK_T004
- bool "AUXTEK_T004"
- depends on MACH_SUN5I
-
-config TARGET_BANANAPI
- bool "BANANAPI"
- depends on MACH_SUN7I
-
-config TARGET_BANANAPRO
- bool "BANANAPRO"
- depends on MACH_SUN7I
-
-config TARGET_COLOMBUS
- bool "COLOMBUS"
- depends on MACH_SUN6I
-
-config TARGET_CUBIEBOARD2
- bool "CUBIEBOARD2"
- depends on MACH_SUN7I
-
-config TARGET_CUBIEBOARD
- bool "CUBIEBOARD"
- depends on MACH_SUN4I
-
-config TARGET_CUBIETRUCK
- bool "CUBIETRUCK"
- depends on MACH_SUN7I
-
-config TARGET_HUMMINGBIRD_A31
- bool "HUMMINGBIRD_A31"
- depends on MACH_SUN6I
-
-config TARGET_IPPO_Q8H_V5
- bool "IPPO_Q8H_V5"
- depends on MACH_SUN8I
-
-config TARGET_PCDUINO
- bool "PCDUINO"
- depends on MACH_SUN4I
-
-config TARGET_PCDUINO3
- bool "PCDUINO3"
- depends on MACH_SUN7I
-
-config TARGET_MELE_A1000G
- bool "MELE_A1000G"
- depends on MACH_SUN4I
-
-config TARGET_MELE_A1000
- bool "MELE_A1000"
- depends on MACH_SUN4I
-
-config TARGET_MELE_M3
- bool "MELE_M3"
- depends on MACH_SUN7I
-
-config TARGET_MELE_M9
- bool "MELE_M9"
- depends on MACH_SUN6I
-
-config TARGET_MINI_X_1GB
- bool "MINI_X_1GB"
- depends on MACH_SUN4I
-
-config TARGET_MINI_X
- bool "MINI_X"
- depends on MACH_SUN4I
-
-config TARGET_MSI_PRIMO73
- bool "MSI Primo73 (7\" tablet)"
- depends on MACH_SUN7I
- ---help---
- The MSI Primo73 is an A20 based tablet, with 1G RAM, 16G NAND,
- 1024x600 TN LCD display, mono speaker, 0.3 MP front camera, 2.0 MP
- rear camera, 3000 mAh battery, gt911 touchscreen, mma8452 accelerometer
- and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons
- (both volume buttons are also connected to the UBOOT_SEL pin). The
- external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB
- OTG and 3.5mm headphone jack. More details are available at
- http://linux-sunxi.org/MSI_Primo73
-
-config TARGET_MSI_PRIMO81
- bool "MSI Primo81 (7.85\" tablet)"
- depends on MACH_SUN6I
- ---help---
- The MSI Primo81 is an A31s based tablet, with 1G RAM, 16G NAND,
- 1024x768 IPS LCD display, mono speaker, 0.3 MP front camera, 2.0 MP
- rear camera, 3500 mAh battery, gt911 touchscreen, mma8452 accelerometer
- and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons
- (both volume buttons are also connected to the UBOOT_SEL pin). The
- external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB
- OTG and 3.5mm headphone jack. More details are available at
- http://linux-sunxi.org/MSI_Primo81
-
-config TARGET_BA10_TV_BOX
- bool "BA10_TV_BOX"
- depends on MACH_SUN4I
-
-config TARGET_I12_TVBOX
- bool "I12_TVBOX"
- depends on MACH_SUN7I
-
-config TARGET_QT840A
- bool "QT840A"
- depends on MACH_SUN7I
-
-config TARGET_R7DONGLE
- bool "R7DONGLE"
- depends on MACH_SUN5I
-
-endchoice
-
config SYS_BOARD
default "sunxi"
@@ -321,6 +260,16 @@ config VIDEO_VGA_VIA_LCD
LCD interface driving a VGA connector, such as found on the
Olimex A13 boards.
+config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
+ boolean "Force sync active high for VGA via LCD controller support"
+ depends on VIDEO_VGA_VIA_LCD
+ default n
+ ---help---
+ Say Y here if you've a board which uses opendrain drivers for the vga
+ hsync and vsync signals. Opendrain drivers cannot generate steep enough
+ positive edges for a stable video output, so on boards with opendrain
+ drivers the sync signals must always be active high.
+
config VIDEO_VGA_EXTERNAL_DAC_EN
string "LCD panel power enable pin"
depends on VIDEO_VGA_VIA_LCD
@@ -338,6 +287,13 @@ config VIDEO_LCD_MODE
This is in drivers/video/videomodes.c: video_get_params() format, e.g.
x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
+config VIDEO_LCD_DCLK_PHASE
+ int "LCD panel display clock phase"
+ depends on VIDEO
+ default 1
+ ---help---
+ Select LCD panel display clock phase shift, range 0-3.
+
config VIDEO_LCD_POWER
string "LCD panel power enable pin"
depends on VIDEO
@@ -363,6 +319,13 @@ config VIDEO_LCD_BL_PWM
Set the backlight pwm pin for the LCD panel. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+config VIDEO_LCD_BL_PWM_ACTIVE_LOW
+ bool "LCD panel backlight pwm is inverted"
+ depends on VIDEO
+ default y
+ ---help---
+ Set this if the backlight pwm output is active low.
+
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
@@ -387,9 +350,32 @@ config VIDEO_LCD_PANEL_LVDS
bool "Generic lvds interface LCD panel"
select VIDEO_LCD_IF_LVDS
+config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
+ bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
+ select VIDEO_LCD_SSD2828
+ select VIDEO_LCD_IF_PARALLEL
+ ---help---
+ 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
+
+config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
+ bool "Hitachi tx18d42vm LCD panel"
+ select VIDEO_LCD_HITACHI_TX18D42VM
+ select VIDEO_LCD_IF_LVDS
+ ---help---
+ 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
+
endchoice
+config USB_MUSB_SUNXI
+ bool "Enable sunxi OTG / DRC USB controller in host mode"
+ default n
+ ---help---
+ Say y here to enable support for the sunxi OTG / DRC USB controller
+ used on almost all sunxi boards. Note currently u-boot can only have
+ one usb host controller enabled at a time, so enabling this on boards
+ which also use the ehci host controller will result in build errors.
+
config USB_KEYBOARD
boolean "Enable USB keyboard support"
default y
@@ -397,4 +383,10 @@ config USB_KEYBOARD
Say Y here to add support for using a USB keyboard (typically used
in combination with a graphical console).
+config GMAC_TX_DELAY
+ int "GMAC Transmit Clock Delay Chain"
+ default 0
+ ---help---
+ Set the GMAC Transmit Clock Delay Chain value.
+
endif