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-rw-r--r--board/solidcard3/init.S55
-rw-r--r--board/solidcard3/sc3nand.c94
-rw-r--r--board/solidcard3/solidcard3.c8
3 files changed, 125 insertions, 32 deletions
diff --git a/board/solidcard3/init.S b/board/solidcard3/init.S
index 36039e8..e7b3c83 100644
--- a/board/solidcard3/init.S
+++ b/board/solidcard3/init.S
@@ -1,26 +1,26 @@
/*------------------------------------------------------------------------------+
*
- * This souce code has been made available to you by EuroDesign
- * (www.eurodsn.de). It's based on the original IBM source code, so
- * this follows:
+ * This souce code has been made available to you by EuroDesign
+ * (www.eurodsn.de). It's based on the original IBM source code, so
+ * this follows:
*
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
*
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
*
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
*
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*------------------------------------------------------------------------------- */
#include <config.h>
@@ -56,12 +56,12 @@ ext_bus_cntlr_init:
* timings into internal flash and external flash
*/
mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
- 0 0 -> 8 bit external ROM
- 0 1 -> 16 bit internal ROM */
+ 0 0 -> 8 bit external ROM
+ 0 1 -> 16 bit internal ROM */
addi r4,0,2
srw r24,r24,r4 /* shift right r24 two positions */
andi. r24,r24,0x06000
-/*
+/*
* All calculations are based on 33MHz EBC clock.
*
* First, create a "very slow" timing (~250ns) with burst mode enabled
@@ -130,7 +130,7 @@ ext_bus_cntlr_init:
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
- * Memory Bank 3 (Second-Flash) initialization
+ * Memory Bank 3 (Second-Flash) initialization
* 0xF0000000...0xF01FFFFF -> 2MB
*----------------------------------------------------------------------- */
@@ -149,7 +149,7 @@ ext_bus_cntlr_init:
xori r24,r24,0x2000 /* invert current bus width */
or r4,r4,r24
mtdcr ebccfgd,r4
-
+
/*-----------------------------------------------------------------------
* Memory Bank 1 (NAND-Flash) initialization
* 0x77D00000...0x77DFFFFF -> 1MB
@@ -186,7 +186,7 @@ ext_bus_cntlr_init:
li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
mtdcr ebccfga,r4
lis r4,0x0180
- ori r4,r4,0x5940
+ ori r4,r4,0x5940
mtdcr ebccfgd,r4
#endif
@@ -199,7 +199,7 @@ ext_bus_cntlr_init:
A7 (ppc notation) or A24 (standard notation) decides about
the type of access:
A7/A24=0 -> memory cycle
- A7//A24=1 -> I/O cycle
+ A7/ /A24=1 -> I/O cycle
*/
li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */
mtdcr ebccfga,r4
@@ -253,7 +253,7 @@ ext_bus_cntlr_init:
li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7401
- ori r4,r4,0xA000
+ ori r4,r4,0xA000
mtdcr ebccfgd,r4
li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */
@@ -295,8 +295,8 @@ ext_bus_cntlr_init:
*
* Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
*
- * |- 300ns --|
- * |---- 420ns ---|---- 420ns ---| cycle
+ * |- 300ns --|
+ * |---- 420ns ---|---- 420ns ---| cycle
* CS ############:###____#######:###____#######
* OE ############:####___#######:####___#######
* WE ############:####__########:####__########
@@ -380,4 +380,3 @@ ext_bus_cntlr_init:
stb r3,0(r4) /* 01 -> external bus controller is initialized */
nop /* pass2 DCR errata #8 */
blr
-
diff --git a/board/solidcard3/sc3nand.c b/board/solidcard3/sc3nand.c
new file mode 100644
index 0000000..7daa877
--- /dev/null
+++ b/board/solidcard3/sc3nand.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/processor.h>
+
+#define readb(addr) *(volatile u_char *)(addr)
+#define readl(addr) *(volatile u_long *)(addr)
+#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
+
+#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
+#define SC3_NAND_CLE 30 /* GPIO PIN 2 */
+#define SC3_NAND_CE 27 /* GPIO PIN 5 */
+
+static void *sc3_io_base;
+static void *sc3_control_base = (void *)0xEF600700;
+
+static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ set_bit (SC3_NAND_CLE, sc3_control_base);
+ break;
+ case NAND_CTL_CLRCLE:
+ clear_bit (SC3_NAND_CLE, sc3_control_base);
+ break;
+
+ case NAND_CTL_SETALE:
+ set_bit (SC3_NAND_ALE, sc3_control_base);
+ break;
+ case NAND_CTL_CLRALE:
+ clear_bit (SC3_NAND_ALE, sc3_control_base);
+ break;
+
+ case NAND_CTL_SETNCE:
+ set_bit (SC3_NAND_CE, sc3_control_base);
+ break;
+ case NAND_CTL_CLRNCE:
+ clear_bit (SC3_NAND_CE, sc3_control_base);
+ break;
+ }
+}
+
+static int sc3_nand_dev_ready(struct mtd_info *mtd)
+{
+ if (!(readl(sc3_control_base + 0x1C) & 0x4000))
+ return 0;
+ return 1;
+}
+
+static void sc3_select_chip(struct mtd_info *mtd, int chip)
+{
+ clear_bit (SC3_NAND_CE, sc3_control_base);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->eccmode = NAND_ECC_SOFT;
+
+ sc3_io_base = (void *) CFG_NAND_BASE;
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
+ nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
+ /* Reference hardware control function */
+ nand->hwcontrol = sc3_nand_hwcontrol;
+ nand->dev_ready = sc3_nand_dev_ready;
+ nand->select_chip = sc3_select_chip;
+ return 0;
+}
+#endif
diff --git a/board/solidcard3/solidcard3.c b/board/solidcard3/solidcard3.c
index 8044711..21cc031 100644
--- a/board/solidcard3/solidcard3.c
+++ b/board/solidcard3/solidcard3.c
@@ -1,4 +1,4 @@
-/*
+/*
* (C) Copyright 2007
* Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
*
@@ -454,7 +454,7 @@ static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
printf("\n -Address setup %luns",
((ap & 0xC0000) >> 18) * CYCLE);
printf("\n -CS active to RD %luns/WR %luns",
- ((ap & 0x30000) >> 16) * CYCLE,
+ ((ap & 0x30000) >> 16) * CYCLE,
((ap & 0xC000) >> 14) * CYCLE);
printf("\n -WR to CS inactive %luns",
((ap & 0x3000) >> 12) * CYCLE);
@@ -496,7 +496,7 @@ int checkboard (void)
for (i = 0; i < 8; i++) {
show_reg (i);
}
-
+
mtdcr (ebccfga, epcr);
ul1 = mfdcr (ebccfgd);
@@ -707,7 +707,7 @@ static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev
switch (PCI_DEV(dev)) {
case 10:
- int_line = 31; /* INT A */
+ int_line = 31; /* INT A */
POST_OUT(0x42);
break;
generated by cgit v1.1 at 2024-12-13 04:37:26 +0000