diff options
Diffstat (limited to 'board/socrates')
| -rw-r--r-- | board/socrates/ddr.c | 7 | ||||
| -rw-r--r-- | board/socrates/law.c | 14 | ||||
| -rw-r--r-- | board/socrates/nand.c | 2 | ||||
| -rw-r--r-- | board/socrates/sdram.c | 32 | ||||
| -rw-r--r-- | board/socrates/socrates.c | 118 | ||||
| -rw-r--r-- | board/socrates/tlb.c | 26 |
6 files changed, 101 insertions, 98 deletions
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index bbb5ee2..2b62b84 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: @@ -57,7 +60,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) * - frequency * - ddr1 vs. ddr2 */ - popts->cpo_override = 10; + popts->cpo_override = 0; /* * Factors to consider for write data delay: diff --git a/board/socrates/law.c b/board/socrates/law.c index 89b446f..71cff8c 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -47,14 +47,14 @@ */ struct law_entry law_table[] = { - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), -#if defined(CFG_FPGA_BASE) - SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), +#if defined(CONFIG_SYS_FPGA_BASE) + SET_LAW(CONFIG_SYS_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CFG_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 6ec53f8..7d76f42 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -23,7 +23,7 @@ #include <common.h> -#if defined(CFG_NAND_BASE) +#if defined(CONFIG_SYS_NAND_BASE) #include <nand.h> #include <asm/errno.h> #include <asm/io.h> diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 12d1b8a..029ba02 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -41,7 +41,7 @@ */ long int sdram_setup(int casl) { - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); /* * Disable memory controller. @@ -49,28 +49,28 @@ long int sdram_setup(int casl) ddr->cs0_config = 0; ddr->sdram_cfg = 0; - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2; - ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; asm ("sync;isync;msync"); udelay(1000); - ddr->sdram_cfg = CFG_DDR_CONFIG; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; asm ("sync; isync; msync"); udelay(1000); - if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) { + if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { /* * OK, size detected -> all done */ - return CFG_SDRAM_SIZE<<20; + return CONFIG_SYS_SDRAM_SIZE<<20; } return 0; /* nothing found ! */ @@ -90,11 +90,11 @@ phys_size_t initdram (int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf ("SDRAM test phase 1:\n"); diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 0991177..d83dc7d 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -51,7 +51,7 @@ ulong flash_get_size (ulong base, int banknum); int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); char *src; int f; @@ -87,7 +87,7 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -98,20 +98,20 @@ int misc_init_r (void) /* * Check if boot FLASH isn't max size */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); + if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { + memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff); + memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff); /* * Re-check to get correct base address */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); } /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { memctl->or1 = 0; memctl->br1 = 0; @@ -120,24 +120,24 @@ int misc_init_r (void) */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR, CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); } return 0; @@ -148,12 +148,12 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; - uint lcrr = CFG_LBC_LCRR; + uint lcrr = CONFIG_SYS_LBC_LCRR; get_sys_info (&sysinfo); clkdiv = lbc->lcrr & 0x0f; @@ -219,7 +219,7 @@ void pci_init_board (void) #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* set and reset the GPIO pin 2 which will reset the W83782G chip */ out_8((unsigned char*)&gur->gpoutdr, 0x3F ); @@ -246,19 +246,19 @@ ft_board_setup(void *blob, bd_t *bd) val[i++] = gd->bd->bi_flashstart; val[i++] = gd->bd->bi_flashsize; - if (mb862xx.frameAdrs == CFG_LIME_BASE) { + if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { /* Fixup LIME mapping */ val[i++] = 2; /* chip select number */ val[i++] = 0; /* always 0 */ - val[i++] = CFG_LIME_BASE; - val[i++] = CFG_LIME_SIZE; + val[i++] = CONFIG_SYS_LIME_BASE; + val[i++] = CONFIG_SYS_LIME_SIZE; } /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ - val[i++] = CFG_FPGA_BASE; - val[i++] = CFG_FPGA_SIZE; + val[i++] = CONFIG_SYS_FPGA_BASE; + val[i++] = CONFIG_SYS_FPGA_SIZE; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); @@ -268,14 +268,14 @@ ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -#define CFG_LIME_SRST ((CFG_LIME_BASE) + 0x01FC002C) -#define CFG_LIME_CCF ((CFG_LIME_BASE) + 0x01FC0038) -#define CFG_LIME_MMR ((CFG_LIME_BASE) + 0x01FCFFFC) +#define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C) +#define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038) +#define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC) /* Lime clock frequency */ -#define CFG_LIME_CLK_100MHZ 0x00000 -#define CFG_LIME_CLK_133MHZ 0x10000 +#define CONFIG_SYS_LIME_CLK_100MHZ 0x00000 +#define CONFIG_SYS_LIME_CLK_133MHZ 0x10000 /* SDRAM parameter */ -#define CFG_LIME_MMR_VALUE 0x4157BA63 +#define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63 #define DISPLAY_WIDTH 800 #define DISPLAY_HEIGHT 480 @@ -308,11 +308,11 @@ const gdc_regs *board_get_regs (void) return init_regs; } -#define CFG_LIME_CID ((CFG_LIME_BASE) + 0x01FC00F0) -#define CFG_LIME_REV ((CFG_LIME_BASE) + 0x01FF8084) +#define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0) +#define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084) int lime_probe(void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint cfg_br2; uint cfg_or2; uint reg; @@ -323,14 +323,14 @@ int lime_probe(void) /* Configure GPCM for CS2 */ memctl->br2 = 0; memctl->or2 = 0xfc000410; - memctl->br2 = (CFG_LIME_BASE) | 0x00001901; + memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; /* Try to access GDC ID/Revision registers */ - reg = in_be32((void *)CFG_LIME_CID); - reg = in_be32((void *)CFG_LIME_CID); + reg = in_be32((void *)CONFIG_SYS_LIME_CID); + reg = in_be32((void *)CONFIG_SYS_LIME_CID); if (reg == 0x303) { - reg = in_be32((void *)CFG_LIME_REV); - reg = in_be32((void *)CFG_LIME_REV); + reg = in_be32((void *)CONFIG_SYS_LIME_REV); + reg = in_be32((void *)CONFIG_SYS_LIME_REV); reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0; } else reg = 0; @@ -351,22 +351,22 @@ unsigned int board_video_init (void) /* * Reset Lime controller */ - out_be32((void *)CFG_LIME_SRST, 0x1); + out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1); udelay(200); /* Set Lime clock to 133MHz */ - out_be32((void *)CFG_LIME_CCF, CFG_LIME_CLK_133MHZ); + out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ); /* Delay required */ udelay(300); /* Set memory parameters */ - out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); + out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); mb862xx.winSizeX = DISPLAY_WIDTH; mb862xx.winSizeY = DISPLAY_HEIGHT; mb862xx.gdfIndex = GDF_15BIT_555RGB; mb862xx.gdfBytesPP = 2; - return CFG_LIME_BASE; + return CONFIG_SYS_LIME_BASE; } #define W83782D_REG_CFG 0x40 @@ -381,22 +381,22 @@ static int w83782d_hwmon_init(void) { u8 buf; - if (i2c_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) + if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) return -1; - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); - buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, + buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, buf | 0x80); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); - buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, + buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, (buf & 0xf4) | 0x01); return 0; } @@ -408,37 +408,37 @@ static void board_backlight_brightness(int br) u8 old_buf; /* Select bank 0 */ - if (i2c_read(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) goto err; else buf = old_buf & 0xf8; - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) goto err; if (br > 0) { /* PWMOUT1 duty cycle ctrl */ buf = 255 / (100 / br); - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) goto err; /* LEDs on */ - reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); if (!(reg & BACKLIGHT_ENABLE)); - out_be32((void *)(CFG_FPGA_BASE + 0x0c), + out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg | BACKLIGHT_ENABLE); } else { buf = 0; - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) goto err; /* LEDs off */ - reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); reg &= ~BACKLIGHT_ENABLE; - out_be32((void *)(CFG_FPGA_BASE + 0x0c), reg); + out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); } /* Restore previous bank setting */ - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) goto err; return; diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index d255cea..b91b1ea 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -31,16 +31,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -50,7 +50,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), @@ -58,7 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -66,16 +66,16 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -#if defined(CFG_FPGA_BASE) +#if defined(CONFIG_SYS_FPGA_BASE) /* * TLB 4: 1M Non-cacheable, guarded * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1M, 1), #endif @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * (0xcbfc0000 256K LIME GDC MMIO) * MMIO is relocatable and could be at 0xcbfc0000 */ - SET_TLB_ENTRY(1, CFG_LIME_BASE, CFG_LIME_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -107,11 +107,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), }; 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