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-rw-r--r--board/socrates/law.c15
-rw-r--r--board/socrates/socrates.c8
-rw-r--r--board/socrates/tlb.c25
3 files changed, 23 insertions, 25 deletions
diff --git a/board/socrates/law.c b/board/socrates/law.c
index 5f4b8ca..ab9a994 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -33,13 +33,12 @@
/*
* LAW(Local Access Window) configuration:
*
- * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x0000_0000 0x2fff_ffff DDR 512M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xc000_0000 0xc00f_ffff FPGA 1M
+ * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR)
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf800_0000 0xf80f_ffff BCSR 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * 0xfc00_0000 0xffff_ffff FLASH 64M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
@@ -49,9 +48,11 @@
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+#if defined(CFG_FPGA_BASE)
+ SET_LAW_ENTRY(5, CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 3c1e826..a75e0c3 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -37,6 +37,9 @@
#include <fdt_support.h>
#include <asm/io.h>
+#if defined(CFG_FPGA_BASE)
+#include "upm_table.h"
+#endif
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
@@ -76,7 +79,10 @@ int checkboard (void)
* Initialize local bus.
*/
local_bus_init ();
-
+#if defined(CFG_FPGA_BASE)
+ /* Init UPMA for FPGA access */
+ upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
+#endif
return 0;
}
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index b80caea..aea99ad 100644
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
- * TLB 0, 1: 128M Non-cacheable, guarded
- * 0xf8000000 128M FLASH
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 64M FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
@@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
+#if defined(CFG_FPGA_BASE)
/*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
+ * TLB 4: 1M Non-cacheable, guarded
+ * 0xc0000000 1M FPGA and NAND
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
+ 0, 4, BOOKE_PAGESZ_1M, 1),
+#endif
/*
* TLB 6: 64M Non-cacheable, guarded