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-rw-r--r--board/siemens/CCM/ccm.c34
-rw-r--r--board/siemens/IAD210/IAD210.c297
-rw-r--r--board/siemens/SCM/scm.c41
-rw-r--r--board/siemens/pcu_e/pcu_e.c377
4 files changed, 311 insertions, 438 deletions
diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c
index f2283b7..b54f3c1 100644
--- a/board/siemens/CCM/ccm.c
+++ b/board/siemens/CCM/ccm.c
@@ -333,42 +333,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c
index 30adbfc..1243887 100644
--- a/board/siemens/IAD210/IAD210.c
+++ b/board/siemens/IAD210/IAD210.c
@@ -41,12 +41,11 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
- 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
+ 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
_NOT_USED_,
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
@@ -56,46 +55,46 @@ const uint sdram_table[] =
* sequence, which is executed by a RUN command.
*
*/
- 0xFFFAF834, 0xFFE5B435, /* last */
- _NOT_USED_,
+ 0xFFFAF834, 0xFFE5B435, /* last */
+ _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
- 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
- _NOT_USED_,
+ 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
- _NOT_USED_,
+ 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF1AAF804, 0xFFA5F447, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xF1AAF804, 0xFFA5F447, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
- 0xFFAFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xFFAFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* MRS sequence (Offset 38 in UPMA RAM)
*/
- 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
- _NOT_USED_,
+ 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
+ _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
- 0xFFAFFC04, 0xFFAFFC05, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xFFAFFC04, 0xFFAFFC05, /* last */
+ _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
@@ -103,82 +102,84 @@ const uint sdram_table[] =
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile fec_t *fecp = &immap->im_cpm.cp_fec;
- long int size;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+ long int size;
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CFG_MPTPR;
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR;
- memctl->memc_mar = 0x00000088;
+ memctl->memc_mar = 0x00000088;
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+ /*
+ * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
- memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+ memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
- udelay(200);
+ udelay (200);
- /* perform SDRAM initializsation sequence */
+ /* perform SDRAM initializsation sequence */
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
- udelay(1);
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
+ udelay (1);
- memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
- udelay(1);
- memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
- udelay(1);
+ memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
+ udelay (1);
+ memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
+ udelay (1);
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
- udelay (1000);
+ udelay (1000);
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- */
- size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ */
+ size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM,
+ SDRAM_MAX_SIZE);
- udelay (1000);
+ udelay (1000);
- memctl->memc_mamr = CFG_MAMR;
- udelay (1000);
+ memctl->memc_mamr = CFG_MAMR;
+ udelay (1000);
- /*
- * Final mapping
- */
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
- memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
+ /*
+ * Final mapping
+ */
+ memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
+ memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
- udelay(10000);
+ udelay (10000);
- /* prepare pin multiplexing for fast ethernet */
+ /* prepare pin multiplexing for fast ethernet */
- atmLoad();
- fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
- iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
+ atmLoad ();
+ fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
+ iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
- return (size);
+ return (size);
}
/* ------------------------------------------------------------------------- */
@@ -191,46 +192,15 @@ long int initdram (int board_type)
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ memctl->memc_mamr = mamr_value;
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
/*
@@ -239,79 +209,78 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
int checkboard (void)
{
- return (0);
+ return (0);
}
-void board_serial_init(void)
+void board_serial_init (void)
{
- ;/* nothing to do here */
+ ; /* nothing to do here */
}
-void board_ether_init(void)
+void board_ether_init (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile fec_t *fecp = &immap->im_cpm.cp_fec;
- atmLoad();
- fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
- iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
+ atmLoad ();
+ fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
+ iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
}
int board_pre_init (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile iop8xx_t *iop = &immap->im_ioport;
-
- /* configure the LED timing output pins - port A pin 4 */
- iop->iop_papar = 0x0800;
- iop->iop_padir = 0x0800;
-
- /* start timer 2 for the 4hz LED blink rate */
- timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
- timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
- timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
-
- /* chip select for PLD access */
- memctl->memc_br6 = 0x10000401;
- memctl->memc_or6 = 0xFC000908;
-
- /* PLD initial values ( set LEDs, remove reset on LXT) */
-
- *PLD_GCR1_REG = 0x06;
- *PLD_EXT_RES = 0xC0;
- *PLD_EXT_FETH = 0x40;
- *PLD_EXT_LED = 0xFF;
- *PLD_EXT_X21 = 0x04;
- return 0;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+
+ /* configure the LED timing output pins - port A pin 4 */
+ iop->iop_papar = 0x0800;
+ iop->iop_padir = 0x0800;
+
+ /* start timer 2 for the 4hz LED blink rate */
+ timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
+ timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
+ timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
+
+ /* chip select for PLD access */
+ memctl->memc_br6 = 0x10000401;
+ memctl->memc_or6 = 0xFC000908;
+
+ /* PLD initial values ( set LEDs, remove reset on LXT) */
+
+ *PLD_GCR1_REG = 0x06;
+ *PLD_EXT_RES = 0xC0;
+ *PLD_EXT_FETH = 0x40;
+ *PLD_EXT_LED = 0xFF;
+ *PLD_EXT_X21 = 0x04;
+ return 0;
}
-void board_get_enetaddr (uchar *addr)
+void board_get_enetaddr (uchar * addr)
{
- int i;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- unsigned int rccrtmp;
-
- char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04};
-
- for (i=0; i<6; i++)
- addr[i] = default_mac_addr[i];
+ int i;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile cpm8xx_t *cpm = &immap->im_cpm;
+ unsigned int rccrtmp;
- printf("There is an error in the i2c driver .. /n");
- printf("You need to fix it first....../n");
+ char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
- rccrtmp = cpm->cp_rccr;
- cpm->cp_rccr |= 0x0020;
+ for (i = 0; i < 6; i++)
+ addr[i] = default_mac_addr[i];
- i2c_reg_read(0xa0, 0);
- printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
- i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
- i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
+ printf ("There is an error in the i2c driver .. /n");
+ printf ("You need to fix it first....../n");
- cpm->cp_rccr = rccrtmp;
+ rccrtmp = cpm->cp_rccr;
+ cpm->cp_rccr |= 0x0020;
+ i2c_reg_read (0xa0, 0);
+ printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
+ i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+ i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+ i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
+ cpm->cp_rccr = rccrtmp;
}
diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c
index 9467b1f..d832edf 100644
--- a/board/siemens/SCM/scm.c
+++ b/board/siemens/SCM/scm.c
@@ -235,13 +235,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- ulong cnt, val;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
+ ulong maxsize, size;
int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
@@ -291,41 +288,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size((long *)base, maxsize);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
+ *orx_ptr = orx | ~(size - 1);
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (size);
}
/*
diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c
index 08dd975..033cc36 100644
--- a/board/siemens/pcu_e/pcu_e.c
+++ b/board/siemens/pcu_e/pcu_e.c
@@ -32,7 +32,7 @@
static long int dram_size (long int, long int *, long int);
static void puma_status (void);
static void puma_set_mode (int mode);
-static int puma_init_done (void);
+static int puma_init_done (void);
static void puma_load (ulong addr, ulong len);
/* ------------------------------------------------------------------------- */
@@ -42,13 +42,12 @@ static void puma_load (ulong addr, ulong len);
/*
* 50 MHz SDRAM access using UPM A
*/
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
- 0x1ffddc47, /* last */
+ 0x1ffddc47, /* last */
/*
* SDRAM Initialization (offset 5 in UPM RAM)
*
@@ -57,40 +56,40 @@ const uint sdram_table[] =
* sequence, which is executed by a RUN command.
*
*/
- 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
+ 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
+ 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
- 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
+ 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
- 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
- _NOT_USED_,
+ 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xfffffc84, 0xfffffc07, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
@@ -98,8 +97,7 @@ const uint sdram_table[] =
/*
* PUMA access using UPM B
*/
-const uint puma_table[] =
-{
+const uint puma_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
@@ -108,7 +106,7 @@ const uint puma_table[] =
/*
* Precharge and MRS
*/
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
@@ -119,8 +117,8 @@ const uint puma_table[] =
/*
* Single Write. (Offset 18 in UPM RAM)
*/
- 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
- _NOT_USED_,
+ 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
@@ -138,8 +136,8 @@ const uint puma_table[] =
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
@@ -158,115 +156,118 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
-long int
-initdram (int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0, reg;
- int i;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ long int size_b0, reg;
+ int i;
- /*
- * Configure UPMA for SDRAM
- */
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ /*
+ * Configure UPMA for SDRAM
+ */
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_mptpr = CFG_MPTPR;
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = 0x00000088;
+ /* burst length=4, burst type=sequential, CAS latency=2 */
+ memctl->memc_mar = 0x00000088;
- /*
- * Map controller bank 2 to the SDRAM bank at preliminary address.
- */
+ /*
+ * Map controller bank 2 to the SDRAM bank at preliminary address.
+ */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = CFG_OR5_PRELIM;
- memctl->memc_br5 = CFG_BR5_PRELIM;
-#else /* XXX */
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
-#endif /* XXX */
+ memctl->memc_or5 = CFG_OR5_PRELIM;
+ memctl->memc_br5 = CFG_BR5_PRELIM;
+#else /* XXX */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+#endif /* XXX */
- /* initialize memory address register */
- memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
+ /* initialize memory address register */
+ memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
- /* mode initialization (offset 5) */
+ /* mode initialization (offset 5) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay(200); /* 0x8000A105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
-#else /* XXX */
- udelay(200); /* 0x80004105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
-#endif /* XXX */
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+ udelay (200); /* 0x8000A105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
+#else /* XXX */
+ udelay (200); /* 0x80004105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
+#endif /* XXX */
+
+ /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay(1); /* 0x8000A830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
-#else /* XXX */
- udelay(1); /* 0x80004830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
-#endif /* XXX */
+ udelay (1); /* 0x8000A830 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
+#else /* XXX */
+ udelay (1); /* 0x80004830 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
+#endif /* XXX */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay(1); /* 0x8000A106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
-#else /* XXX */
- udelay(1); /* 0x80004106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
-#endif /* XXX */
-
- reg = memctl->memc_mamr;
- reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
- reg |= MAMR_TLFA_4X; /* ... to 4x */
- reg |= MAMR_PTAE; /* enable refresh */
- memctl->memc_mamr = reg;
-
- udelay(200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i=0; i<10; ++i) {
+ udelay (1); /* 0x8000A106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
+#else /* XXX */
+ udelay (1); /* 0x80004106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
+#endif /* XXX */
+
+ reg = memctl->memc_mamr;
+ reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
+ reg |= MAMR_TLFA_4X; /* ... to 4x */
+ reg |= MAMR_PTAE; /* enable refresh */
+ memctl->memc_mamr = reg;
+
+ udelay (200);
+
+ /* Need at least 10 DRAM accesses to stabilize */
+ for (i = 0; i < 10; ++i) {
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
-#else /* XXX */
- volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
-#endif /* XXX */
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
+ volatile unsigned long *addr =
+ (volatile unsigned long *) SDRAM_BASE5_PRELIM;
+#else /* XXX */
+ volatile unsigned long *addr =
+ (volatile unsigned long *) SDRAM_BASE2_PRELIM;
+#endif /* XXX */
+ unsigned long val;
+
+ val = *(addr + i);
+ *(addr + i) = val;
+ }
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
-#else /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-#endif /* XXX */
+ size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+#else /* XXX */
+ size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+#endif /* XXX */
- memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
+ memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
- /*
- * Final mapping:
- */
+ /*
+ * Final mapping:
+ */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#else /* XXX */
- memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#endif /* XXX */
- udelay(1000);
-
- /*
- * Configure UPMB for PUMA
- */
- upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
-
- return (size_b0);
+ memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
+ memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+#else /* XXX */
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
+ memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+#endif /* XXX */
+ udelay (1000);
+
+ /*
+ * Configure UPMB for PUMA
+ */
+ upmconfig (UPMB, (uint *) puma_table,
+ sizeof (puma_table) / sizeof (uint));
+
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
@@ -279,119 +280,88 @@ initdram (int board_type)
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
- val = *addr;
- *addr = save[--i];
+ memctl->memc_mamr = mamr_value;
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
-#else /* XXX */
+#else /* XXX */
#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
#endif /* XXX */
#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
-void reset_phy(void)
+void reset_phy (void)
{
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *) CFG_IMMR;
ulong value;
/* Configure all needed port pins for GPIO */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
# if CFG_ETH_MDDIS_VALUE
- immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
+ immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
# else
immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
# endif
immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
- immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
+ immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
#endif /* XXX */
immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
- value = immr->im_cpm.cp_pbdat;
+ value = immr->im_cpm.cp_pbdat;
/* Assert Powerdown and Reset signals */
- value |= CFG_PB_ETH_POWERDOWN;
+ value |= CFG_PB_ETH_POWERDOWN;
value &= ~(CFG_PB_ETH_RESET);
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
# if CFG_ETH_MDDIS_VALUE
- value |= CFG_PB_ETH_MDDIS;
+ value |= CFG_PB_ETH_MDDIS;
# else
value &= ~(CFG_PB_ETH_MDDIS);
# endif
#endif
#if CFG_ETH_CFG1_VALUE
- value |= CFG_PB_ETH_CFG1;
+ value |= CFG_PB_ETH_CFG1;
#else
value &= ~(CFG_PB_ETH_CFG1);
#endif
#if CFG_ETH_CFG2_VALUE
- value |= CFG_PB_ETH_CFG2;
+ value |= CFG_PB_ETH_CFG2;
#else
value &= ~(CFG_PB_ETH_CFG2);
#endif
#if CFG_ETH_CFG3_VALUE
- value |= CFG_PB_ETH_CFG3;
+ value |= CFG_PB_ETH_CFG3;
#else
value &= ~(CFG_PB_ETH_CFG3);
#endif
/* Drive output signals to initial state */
- immr->im_cpm.cp_pbdat = value;
+ immr->im_cpm.cp_pbdat = value;
immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
udelay (10000);
/* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+ immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
udelay (10000);
/* de-assert RESET signal of PHY */
- immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
+ immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
udelay (1000);
}
@@ -403,23 +373,23 @@ void reset_phy(void)
#define PUMA_READ_MODE 0
#define PUMA_LOAD_MODE 1
-int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong addr, len;
switch (argc) {
- case 2: /* PUMA reset */
- if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
+ case 2: /* PUMA reset */
+ if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
puma_status ();
return 0;
}
break;
- case 4: /* PUMA load addr len */
- if (strcmp(argv[1],"load") != 0)
+ case 4: /* PUMA load addr len */
+ if (strcmp (argv[1], "load") != 0)
break;
- addr = simple_strtoul(argv[2], NULL, 16);
- len = simple_strtoul(argv[3], NULL, 16);
+ addr = simple_strtoul (argv[2], NULL, 16);
+ len = simple_strtoul (argv[3], NULL, 16);
printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
addr, len, len);
@@ -432,47 +402,46 @@ int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
-U_BOOT_CMD(
- puma, 4, 1, do_puma,
- "puma - access PUMA FPGA\n",
- "status - print PUMA status\n"
- "puma load addr len - load PUMA configuration data\n"
-);
-#endif /* CFG_CMD_BSP */
+U_BOOT_CMD (puma, 4, 1, do_puma,
+ "puma - access PUMA FPGA\n",
+ "status - print PUMA status\n"
+ "puma load addr len - load PUMA configuration data\n");
+
+#endif /* CFG_CMD_BSP */
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static void puma_set_mode (int mode)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* disable PUMA in memory controller */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_br3 = 0;
-#else /* XXX */
- memctl->memc_br4 = 0;
-#endif /* XXX */
+ memctl->memc_br3 = 0;
+#else /* XXX */
+ memctl->memc_br4 = 0;
+#endif /* XXX */
switch (mode) {
case PUMA_READ_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_READ;
memctl->memc_br3 = PUMA_CONF_BR_READ;
-#else /* XXX */
+#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
+#endif /* XXX */
break;
case PUMA_LOAD_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_LOAD;
memctl->memc_br3 = PUMA_CONF_BR_LOAD;
-#else /* XXX */
+#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
+#endif /* XXX */
break;
}
}
@@ -483,9 +452,9 @@ static void puma_set_mode (int mode)
static void puma_load (ulong addr, ulong len)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
- uchar *data = (uchar *)addr;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
+ uchar *data = (uchar *) addr;
int i;
/* align length */
@@ -497,7 +466,7 @@ static void puma_load (ulong addr, ulong len)
immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
@@ -510,14 +479,14 @@ static void puma_load (ulong addr, ulong len)
#endif /* XXX */
udelay (100);
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
#else
- immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
+ immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
#endif /* XXX */
/* wait until INIT indicates completion of reset */
- for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
+ for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
udelay (1000);
if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
break;
@@ -543,18 +512,18 @@ static void puma_status (void)
{
/* Check state */
printf ("PUMA initialization is %scomplete\n",
- puma_init_done() ? "" : "NOT ");
+ puma_init_done ()? "" : "NOT ");
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static int puma_init_done (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
/* make sure pin is GPIO input */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
- immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
@@ -565,20 +534,20 @@ static int puma_init_done (void)
int misc_init_r (void)
{
ulong addr = 0;
- ulong len = 0;
+ ulong len = 0;
char *s;
printf ("PUMA: ");
- if (puma_init_done()) {
+ if (puma_init_done ()) {
printf ("initialized\n");
return 0;
}
- if ((s = getenv("puma_addr")) != NULL)
- addr = simple_strtoul(s, NULL, 16);
+ if ((s = getenv ("puma_addr")) != NULL)
+ addr = simple_strtoul (s, NULL, 16);
- if ((s = getenv("puma_len")) != NULL)
- len = simple_strtoul(s, NULL, 16);
+ if ((s = getenv ("puma_len")) != NULL)
+ len = simple_strtoul (s, NULL, 16);
if ((!addr) || (!len)) {
printf ("net list undefined\n");
generated by cgit v1.1 at 2024-11-28 09:03:36 +0000