diff options
Diffstat (limited to 'board/siemens')
| -rw-r--r-- | board/siemens/IAD210/IAD210.c | 318 | ||||
| -rw-r--r-- | board/siemens/SCM/scm.c | 573 | ||||
| -rw-r--r-- | board/siemens/pcu_e/pcu_e.c | 589 |
3 files changed, 1480 insertions, 0 deletions
diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c new file mode 100644 index 0000000..4897046 --- /dev/null +++ b/board/siemens/IAD210/IAD210.c @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2001 + * Paul Geerinckx + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> +#include "atm.h" +#include <i2c.h> + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +/* used PLD registers */ +# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0) +# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10) +# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11) +# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12) +# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13) + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */ + _NOT_USED_, + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0xFFFAF834, 0xFFE5B435, /* last */ + _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00, + 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, + 0xF1AAF804, 0xFFA5F447, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84, + 0xFFAFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * MRS sequence (Offset 38 in UPMA RAM) + */ + 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */ + _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0xFFAFFC04, 0xFFAFFC05, /* last */ + _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile iop8xx_t *iop = &immap->im_ioport; + volatile fec_t *fecp = &immap->im_cpm.cp_fec; + long int size; + + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + + memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay(1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay(1); + + memctl->memc_mcr = 0x80004105; /* SDRAM precharge */ + udelay(1); + memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */ + udelay(1); + memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */ + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + */ + size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); + + udelay (1000); + + + memctl->memc_mamr = CFG_MAMR; + udelay (1000); + + /* + * Final mapping + */ + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM; + memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); + + udelay(10000); + + /* prepare pin multiplexing for fast ethernet */ + + atmLoad(); + fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ + iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ + + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof(long)); + } + } + return (maxsize); +} + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + return (0); +} + +void board_serial_init(void) +{ + ;/* nothing to do here */ +} + +void board_ether_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile iop8xx_t *iop = &immap->im_ioport; + volatile fec_t *fecp = &immap->im_cpm.cp_fec; + + atmLoad(); + fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ + iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ +} + +int board_pre_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile iop8xx_t *iop = &immap->im_ioport; + + /* configure the LED timing output pins - port A pin 4 */ + iop->iop_papar = 0x0800; + iop->iop_padir = 0x0800; + + /* start timer 2 for the 4hz LED blink rate */ + timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */ + timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */ + timers->cpmt_tgcr = 0x00000810; /* run timer 2 */ + + /* chip select for PLD access */ + memctl->memc_br6 = 0x10000401; + memctl->memc_or6 = 0xFC000908; + + /* PLD initial values ( set LEDs, remove reset on LXT) */ + + *PLD_GCR1_REG = 0x06; + *PLD_EXT_RES = 0xC0; + *PLD_EXT_FETH = 0x40; + *PLD_EXT_LED = 0xFF; + *PLD_EXT_X21 = 0x04; + return 0; +} + +void board_get_enetaddr (uchar *addr) +{ + int i; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpm = &immap->im_cpm; + unsigned int rccrtmp; + + char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04}; + + for (i=0; i<6; i++) + addr[i] = default_mac_addr[i]; + + printf("There is an error in the i2c driver .. /n"); + printf("You need to fix it first....../n"); + + rccrtmp = cpm->cp_rccr; + cpm->cp_rccr |= 0x0020; + + i2c_reg_read(0xa0, 0); + printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n", + i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), + i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) ); + + cpm->cp_rccr = rccrtmp; + + +} diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c new file mode 100644 index 0000000..aa6181d --- /dev/null +++ b/board/siemens/SCM/scm.c @@ -0,0 +1,573 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc8260.h> + +#include "scm.h" + +static void config_scoh_cs(void); +extern int fpga_init(void); + +#if 0 +#define DEBUGF(fmt,args...) printf (fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, + /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */ + /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */ + /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */ + /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */ + /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */ + /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */ + /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */ + /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, + /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */ + /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */ + /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */ + /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */ + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, + /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */ + /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */ + /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */ + /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */ + /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */ + /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */ + /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */ + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */ + /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */ + /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */ + /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */ + /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */ + /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC19 */ { 0, 1, 0, 0, 0, 0 }, + /* PC18 */ { 0, 1, 0, 0, 0, 0 }, + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, + /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */ + /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */ + }, + + /* Port D configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, + /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */ + /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */ + /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ + /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */ + /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */ + /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */ + /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */ + /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */ + /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */ + /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, + /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */ + /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + unsigned char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (!i || strncmp (str, "TQM8260", 7)) { + puts ("### No HW ID - assuming TQM8260\n"); + return (0); + } + + puts (str); + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + ulong cnt, val; + volatile ulong *addr; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + int i; + ulong save[32]; /* to make test non-destructive */ + ulong maxsize; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; + orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + /* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + i = 0; + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + save[i++] = *addr; + *addr = ~cnt; + } + + addr = (volatile ulong *) base; + save[i] = *addr; + *addr = 0; + + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + /* Write the actual size to ORx + */ + *orx_ptr = orx | ~(cnt * sizeof (long) - 1); + return (cnt * sizeof (long)); + } + } + return (maxsize); +} + +/* + * Test Power-On-Reset. + */ +int power_on_reset (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Test Reset Status Register */ + return gd->reset_status & RSR_CSRS ? 0 : 1; +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + long size8, size9; +#endif + long psize, lsize; + + psize = 16 * 1024 * 1024; + lsize = 0; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#if 0 /* Just for debugging */ +#define prt_br_or(brX,orX) do { \ + ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ + ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ + printf ("\n" \ + #brX " 0x%08x " #orX " 0x%08x " \ + "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ + memctl->memc_ ## brX, memctl->memc_ ## orX, \ + start, start+sizem, (sizem+1)>>20); \ + } while (0) + prt_br_or (br0, or0); + prt_br_or (br1, or1); + prt_br_or (br2, or2); + prt_br_or (br3, or3); +#endif + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL - %ld MB, ", psize >> 20); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL - %ld MB, ", psize >> 20); + } + + /* Local SDRAM setup: + */ +#ifdef CFG_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CFG_LSRT; + size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + (uchar *) SDRAM_BASE2_PRELIM); + + if (size8 < size9) { + lsize = size9; + printf ("Local:9COL - %ld MB) using ", lsize >> 20); + } else { + lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + printf ("Local:8COL - %ld MB) using ", lsize >> 20); + } + +#if 0 + /* Set up BR2 so that the local SDRAM goes + * right after the 60x SDRAM + */ + memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | + (CFG_SDRAM_BASE + psize); +#endif +#endif /* CFG_INIT_LOCAL_SDRAM */ +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + config_scoh_cs (); + + return (psize); +} + +/* ------------------------------------------------------------------------- */ + +static void config_scoh_cs (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE; + volatile uint tmp, i; + + /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ + memctl->memc_or3 = CFG_CAN0_OR3; + memctl->memc_br3 = CFG_CAN0_BR3; + /* Initialize OR4 / BR4 for CAN Bus Controller 1 */ + memctl->memc_or4 = CFG_CAN1_OR4; + memctl->memc_br4 = CFG_CAN1_BR4; + + /* Initialize MAMR to write in the array at address 0x0 */ + memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS; + + /* Initialize UPMA for CAN: single read */ + memctl->memc_mdr = 0xcffeec00; + udelay (1); /* Necessary to have the data correct in the UPM array!!!! */ + /* The read on the CAN controller write the data of mdr in UPMA array. */ + /* The index to the array will be incremented automatically + through this read */ + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcfc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcfc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0xfffdec07; + udelay (1); + tmp = can->cpu_interface; + + + /* Initialize MAMR to write in the array at address 0x18 */ + memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS; + + /* Initialize UPMA for CAN: single write */ + memctl->memc_mdr = 0xfcffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00fffc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00fffc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x30ffec07; + udelay (1); + tmp = can->cpu_interface; + + /* Initialize MAMR */ + memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */ + + + /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */ + memctl->memc_or5 = CFG_EXTPROM_OR5; + memctl->memc_br5 = CFG_EXTPROM_BR5; + /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */ + memctl->memc_or6 = CFG_EXTPROM_OR6; + memctl->memc_br6 = CFG_EXTPROM_BR6; + + /* Initialize OR7 / BR7 for the Glue Logic */ + memctl->memc_or7 = CFG_FIOX_OR7; + memctl->memc_br7 = CFG_FIOX_BR7; + + /* Initialize OR8 / BR8 for the DOH Logic */ + memctl->memc_or8 = CFG_FDOHM_OR8; + memctl->memc_br8 = CFG_FDOHM_BR8; + + DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0); + DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1); + DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2); + DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3); + DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4); + DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5); + DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6); + DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7); + DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8); + + DEBUGF ("UPMA addr 0x0\n"); + memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS; + for (i = 0; i < 0x8; i++) { + tmp = can->cpu_interface; + udelay (1); + DEBUGF (" %08x ", memctl->memc_mdr); + } + DEBUGF ("\nUPMA addr 0x18\n"); + memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS; + for (i = 0; i < 0x8; i++) { + tmp = can->cpu_interface; + udelay (1); + DEBUGF (" %08x ", memctl->memc_mdr); + } + DEBUGF ("\n"); + memctl->memc_mamr = MxMR_GPL_x4DIS; +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r (void) +{ + fpga_init (); + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c new file mode 100644 index 0000000..6c0b5eb --- /dev/null +++ b/board/siemens/pcu_e/pcu_e.c @@ -0,0 +1,589 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> +#include <commproc.h> +#include <i2c.h> +#include <command.h> +#include <cmd_bsp.h> + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +static void puma_status (void); +static void puma_set_mode (int mode); +static int puma_init_done (void); +static void puma_load (ulong addr, ulong len); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +/* + * 50 MHz SDRAM access using UPM A + */ +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00, + 0x1ffddc47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00, + 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + +/* + * PUMA access using UPM B + */ +const uint puma_table[] = +{ + /* + * Single Read. (Offset 0 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, + /* + * Precharge and MRS + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + */ + +int checkboard (void) +{ + puts ("Board: Siemens PCU E\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int +initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + long int size_b0, reg; + int i; + + /* + * Configure UPMA for SDRAM + */ + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = CFG_MPTPR; + + /* burst length=4, burst type=sequential, CAS latency=2 */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 2 to the SDRAM bank at preliminary address. + */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or5 = CFG_OR5_PRELIM; + memctl->memc_br5 = CFG_BR5_PRELIM; +#else /* XXX */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; +#endif /* XXX */ + + /* initialize memory address register */ + memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */ + + /* mode initialization (offset 5) */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + udelay(200); /* 0x8000A105 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05); +#else /* XXX */ + udelay(200); /* 0x80004105 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05); +#endif /* XXX */ + + /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + udelay(1); /* 0x8000A830 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30); +#else /* XXX */ + udelay(1); /* 0x80004830 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30); +#endif /* XXX */ + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + udelay(1); /* 0x8000A106 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06); +#else /* XXX */ + udelay(1); /* 0x80004106 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06); +#endif /* XXX */ + + reg = memctl->memc_mamr; + reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */ + reg |= MAMR_TLFB_4X; /* ... to 4x */ + reg |= MAMR_PTBE; /* enable refresh */ + memctl->memc_mamr = reg; + + udelay(200); + + /* Need at least 10 DRAM accesses to stabilize */ + for (i=0; i<10; ++i) { +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM; +#else /* XXX */ + volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM; +#endif /* XXX */ + unsigned long val; + + val = *(addr + i); + *(addr + i) = val; + } + + /* + * Check Bank 0 Memory Size for re-configuration + */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); +#else /* XXX */ + size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); +#endif /* XXX */ + + memctl->memc_mamr = CFG_MAMR | MAMR_PTBE; + + /* + * Final mapping: + */ + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; + memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; +#else /* XXX */ + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; + memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; +#endif /* XXX */ + udelay(1000); + + /* + * Configure UPMB for PUMA + */ + upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint)); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof(long)); + } + } + return (maxsize); +} + +/* ------------------------------------------------------------------------- */ + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#else /* XXX */ +#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \ + CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#endif /* XXX */ + +#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET) + +void reset_phy(void) +{ + immap_t *immr = (immap_t *)CFG_IMMR; + ulong value; + + /* Configure all needed port pins for GPIO */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +# if CFG_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +# else + immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */ +# endif + immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */ + immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */ +#endif /* XXX */ + immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ + + value = immr->im_cpm.cp_pbdat; + + /* Assert Powerdown and Reset signals */ + value |= CFG_PB_ETH_POWERDOWN; + value &= ~(CFG_PB_ETH_RESET); + + /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ +#if !PCU_E_WITH_SWAPPED_CS +# if CFG_ETH_MDDIS_VALUE + value |= CFG_PB_ETH_MDDIS; +# else + value &= ~(CFG_PB_ETH_MDDIS); +# endif +#endif +#if CFG_ETH_CFG1_VALUE + value |= CFG_PB_ETH_CFG1; +#else + value &= ~(CFG_PB_ETH_CFG1); +#endif +#if CFG_ETH_CFG2_VALUE + value |= CFG_PB_ETH_CFG2; +#else + value &= ~(CFG_PB_ETH_CFG2); +#endif +#if CFG_ETH_CFG3_VALUE + value |= CFG_PB_ETH_CFG3; +#else + value &= ~(CFG_PB_ETH_CFG3); +#endif + + /* Drive output signals to initial state */ + immr->im_cpm.cp_pbdat = value; + immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; + udelay (10000); + + /* De-assert Ethernet Powerdown */ + immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + udelay (10000); + + /* de-assert RESET signal of PHY */ + immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET; + udelay (1000); +} + +/*----------------------------------------------------------------------- + * Board Special Commands: access functions for "PUMA" FPGA + */ +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +#define PUMA_READ_MODE 0 +#define PUMA_LOAD_MODE 1 + +int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, len; + + switch (argc) { + case 2: /* PUMA reset */ + if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */ + puma_status (); + return 0; + } + break; + case 4: /* PUMA load addr len */ + if (strcmp(argv[1],"load") != 0) + break; + + addr = simple_strtoul(argv[2], NULL, 16); + len = simple_strtoul(argv[3], NULL, 16); + + printf ("PUMA load: addr %08lX len %ld (0x%lX): ", + addr, len, len); + puma_load (addr, len); + + return 0; + default: + break; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +#endif /* CFG_CMD_BSP */ + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static void puma_set_mode (int mode) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + /* disable PUMA in memory controller */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_br3 = 0; +#else /* XXX */ + memctl->memc_br4 = 0; +#endif /* XXX */ + + switch (mode) { + case PUMA_READ_MODE: +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or3 = PUMA_CONF_OR_READ; + memctl->memc_br3 = PUMA_CONF_BR_READ; +#else /* XXX */ + memctl->memc_or4 = PUMA_CONF_OR_READ; + memctl->memc_br4 = PUMA_CONF_BR_READ; +#endif /* XXX */ + break; + case PUMA_LOAD_MODE: +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or3 = PUMA_CONF_OR_LOAD; + memctl->memc_br3 = PUMA_CONF_BR_LOAD; +#else /* XXX */ + memctl->memc_or4 = PUMA_CONF_OR_READ; + memctl->memc_br4 = PUMA_CONF_BR_READ; +#endif /* XXX */ + break; + } +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */ + +static void puma_load (ulong addr, ulong len) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */ + uchar *data = (uchar *)addr; + int i; + + /* align length */ + if (len & 1) + ++len; + + /* Reset FPGA */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */ + immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT); + immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT); + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */ + immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */ + immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */ +#else + immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */ + immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */ + immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */ + immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */ +#endif /* XXX */ + udelay (100); + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */ +#else + immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */ +#endif /* XXX */ + + /* wait until INIT indicates completion of reset */ + for (i=0; i<PUMA_INIT_TIMEOUT; ++i) { + udelay (1000); + if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT) + break; + } + if (i == PUMA_INIT_TIMEOUT) { + printf ("*** PUMA init timeout ***\n"); + return; + } + + puma_set_mode (PUMA_LOAD_MODE); + + while (len--) + *fpga_addr = *data++; + + puma_set_mode (PUMA_READ_MODE); + + puma_status (); +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static void puma_status (void) +{ + /* Check state */ + printf ("PUMA initialization is %scomplete\n", + puma_init_done() ? "" : "NOT "); +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static int puma_init_done (void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + /* make sure pin is GPIO input */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE); + immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE); + immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE); + + return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0; +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r (void) +{ + ulong addr = 0; + ulong len = 0; + char *s; + + printf ("PUMA: "); + if (puma_init_done()) { + printf ("initialized\n"); + return 0; + } + + if ((s = getenv("puma_addr")) != NULL) + addr = simple_strtoul(s, NULL, 16); + + if ((s = getenv("puma_len")) != NULL) + len = simple_strtoul(s, NULL, 16); + + if ((!addr) || (!len)) { + printf ("net list undefined\n"); + return 0; + } + + printf ("loading... "); + + puma_load (addr, len); + return (0); +} + +/* ------------------------------------------------------------------------- */ |