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-rw-r--r--board/seco/mx6quq7/mx6quq7.c25
1 files changed, 21 insertions, 4 deletions
diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c
index e7523f1..08566fc 100644
--- a/board/seco/mx6quq7/mx6quq7.c
+++ b/board/seco/mx6quq7/mx6quq7.c
@@ -91,11 +91,30 @@ int board_eth_init(bd_t *bis)
return ret;
}
+#define USDHC4_CD_GPIO IMX_GPIO_NR(2, 6)
+
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR},
- {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR, 0, 4},
+ {USDHC4_BASE_ADDR, 0, 4},
};
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = 1; /* Assume eMMC is always present */
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = !gpio_get_value(USDHC4_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
int board_mmc_init(bd_t *bis)
{
u32 index = 0;
@@ -112,12 +131,10 @@ int board_mmc_init(bd_t *bis)
case 0:
seco_mx6_setup_usdhc_iomux(3);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 4;
break;
case 1:
seco_mx6_setup_usdhc_iomux(4);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- usdhc_cfg[1].max_bus_width = 4;
break;
default: