1 files changed, 0 insertions, 45 deletions
diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S
index 95cb85a..e149fbd 100644
--- a/board/sbc8560/init.S
+++ b/board/sbc8560/init.S
@@ -40,51 +40,6 @@
 	mtlr	r1	;	\
 	blr		;
 
-
-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(512M) -or- larger
- * c000_0000-cfff_ffff: PCI(256M)
- * d000_0000-dfff_ffff: RapidIO(256M)
- * e000_0000-ffff_ffff: localbus(512M)
- *   e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
- *   e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
- *   e800_0000-efff_ffff: LBC 128M, nothing here
- *   f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
- *   f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
- *   f800_0000-fdff_ffff: LBC 64M, nothing here
- *   fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
- *   fd00_0000-fdff_ffff: LBC 16M, nothing here
- *   fe00_0000-feff_ffff: LBC 16M, nothing here
- *   ff00_0000-ff6f_ffff: LBC 7M, nothing here
- *   ff70_0000-ff7f_ffff: CCSRBAR 1M
- *   ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- *       Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-  #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-  #define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#else
-  #define LAWBAR0 0
-  #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR2 ((0xe0000000>>12) & 0xfffff)
-#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-	.section .bootpg, "ax"
-	.globl  law_entry
-law_entry:
-	entry_start
-	.long 0x03
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
-	entry_end
-
 /* TLB1 entries configuration: */
 
 	.section	.bootpg, "ax"