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-rw-r--r--board/sbc8548/sbc8548.c45
-rw-r--r--board/sbc8548/tlb.c34
2 files changed, 13 insertions, 66 deletions
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 06c1eea..1bce6fa 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram (void);
int board_early_init_f (void)
{
@@ -69,47 +67,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- out_be32(&gur->ddrdllcr, 0x81000000);
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
@@ -268,7 +225,7 @@ testdram(void)
* fixed_sdram init -- doesn't use serial presence detect.
* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 38bdeb3..bb4c052 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 1, BOOKE_PAGESZ_1G, 1),
/*
- * TLB 2: 256M Cacheable, non-guarded
- * 0x0 256M DDR SDRAM
- */
-#if !defined(CONFIG_SPD_EEPROM)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-#endif
-
- /*
- * TLB 3: 64M Non-cacheable, guarded
+ * TLB 2: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 8M PCI1 IO
* 0xe2800000 8M PCIe IO
*/
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_64M, 1),
+ 0, 2, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 4: 64M Cacheable, non-guarded
+ * TLB 3: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 4, BOOKE_PAGESZ_64M, 1),
+ 0, 3, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 5: 64M Cacheable, non-guarded
+ * TLB 4: 64M Cacheable, non-guarded
* 0xf4000000 64M LBC SDRAM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_64M, 1),
+ 0, 4, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 6: 16M Cacheable, non-guarded
+ * TLB 5: 16M Cacheable, non-guarded
* 0xf8000000 1M 7-segment LED display
* 0xf8100000 1M User switches
* 0xf8300000 1M Board revision
@@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
+ 0, 5, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 7: 4M Non-cacheable, guarded
+ * TLB 6: 4M Non-cacheable, guarded
* 0xfb800000 4M 1st 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
+ 0, 6, BOOKE_PAGESZ_4M, 1),
/*
- * TLB 8: 4M Non-cacheable, guarded
+ * TLB 7: 4M Non-cacheable, guarded
* 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
CONFIG_SYS_ALT_FLASH + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4M, 1),
+ 0, 7, BOOKE_PAGESZ_4M, 1),
};