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-rw-r--r--board/sbc8548/ddr.c77
-rw-r--r--board/sbc8548/law.c16
-rw-r--r--board/sbc8548/sbc8548.c111
-rw-r--r--board/sbc8548/tlb.c24
4 files changed, 162 insertions, 66 deletions
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 996ffe2..45ec485 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
@@ -54,3 +55,79 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->half_strength_driver_enable = 0;
}
+
+#ifdef CONFIG_SPD_EEPROM
+/*
+ * Workaround for hardware errata. An i2c address conflict
+ * existed on earlier boards; the workaround moved the DDR
+ * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
+ * if that fails, then fall back to reading at 0x51.
+ */
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret;
+
+#ifdef ALT_SPD_EEPROM_ADDRESS
+ if (i2c_address == SPD_EEPROM_ADDRESS) {
+ ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret == 0)
+ return; /* Good data at 0x53 */
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+#endif
+ ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret) {
+ printf("DDR: failed to read SPD from addr %u\n", i2c_address);
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
+
+#else
+/*
+ * fixed_sdram init -- doesn't use serial presence detect.
+ * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ */
+phys_size_t fixed_sdram(void)
+{
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+ out_be32(&ddr->cs0_bnds, 0x0000007f);
+ out_be32(&ddr->cs1_bnds, 0x008000ff);
+ out_be32(&ddr->cs2_bnds, 0x00000000);
+ out_be32(&ddr->cs3_bnds, 0x00000000);
+
+ out_be32(&ddr->cs0_config, 0x80010101);
+ out_be32(&ddr->cs1_config, 0x80010101);
+ out_be32(&ddr->cs2_config, 0x00000000);
+ out_be32(&ddr->cs3_config, 0x00000000);
+
+ out_be32(&ddr->timing_cfg_3, 0x00000000);
+ out_be32(&ddr->timing_cfg_0, 0x00220802);
+ out_be32(&ddr->timing_cfg_1, 0x38377322);
+ out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
+
+ out_be32(&ddr->sdram_cfg, 0x4300C000);
+ out_be32(&ddr->sdram_cfg_2, 0x24401000);
+
+ out_be32(&ddr->sdram_mode, 0x23C00542);
+ out_be32(&ddr->sdram_mode_2, 0x00000000);
+
+ out_be32(&ddr->sdram_interval, 0x05080100);
+ out_be32(&ddr->sdram_md_cntl, 0x00000000);
+ out_be32(&ddr->sdram_data_init, 0x00000000);
+ out_be32(&ddr->sdram_clk_cntl, 0x03800000);
+ asm("sync;isync;msync");
+ udelay(500);
+
+ #ifdef CONFIG_DDR_ECC
+ /* Enable ECC checking */
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
+ #else
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+ #endif
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index 5fa9db0..322af76 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -36,22 +36,36 @@
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe27f_ffff PCI1 IO 8M
* 0xe280_0000 0xe2ff_ffff PCIe IO 8M
+ * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
- * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
*
+ * If swapped CS0/CS6 via JP12+SW2.8:
+ * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
+ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
+ *
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_ALT_BOOT
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+#else
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#endif
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#else
+ /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 26095a5..371d076 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -76,11 +76,15 @@ local_bus_init(void)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint clkdiv;
+ uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
+
+ lbc_mhz = sysinfo.freqLocalBus / 1000000;
+ clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus;
+
+ debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {
@@ -91,10 +95,38 @@ local_bus_init(void)
out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
}
- setbits_be32(&lbc->lcrr, 0x00030000);
+ /*
+ * Local Bus Clock > 83.3 MHz. According to timing
+ * specifications set LCRR[EADC] to 2 delay cycles.
+ */
+ if (lbc_mhz > 83) {
+ lcrr &= ~LCRR_EADC;
+ lcrr |= LCRR_EADC_2;
+ }
+
+ /*
+ * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+ * disable PLL bypass for Local Bus Clock > 83 MHz.
+ */
+ if (lbc_mhz >= 66)
+ lcrr &= (~LCRR_DBYP); /* DLL Enabled */
+
+ else
+ lcrr |= LCRR_DBYP; /* DLL Bypass */
+ out_be32(&lbc->lcrr, lcrr);
asm("sync;isync;msync");
+ /*
+ * According to MPC8548ERMAD Rev.1.3 read back LCRR
+ * and terminate with isync
+ */
+ lcrr = in_be32(&lbc->lcrr);
+ asm ("isync;");
+
+ /* let DLL stabilize */
+ udelay(500);
+
out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
}
@@ -107,13 +139,14 @@ void lbc_sdram_init(void)
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
+ const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint lsdmr_common;
+ uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
puts(" SDRAM: ");
- print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size(size, "\n");
/*
* Setup SDRAM Base and Option Registers
@@ -131,47 +164,49 @@ void lbc_sdram_init(void)
asm("msync");
/*
- * MPC8548 uses "new" 15-16 style addressing.
- */
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= LSDMR_BSMA1516;
-
- /*
* Issue PRECHARGE ALL command.
*/
- out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
}
/*
* Issue 8 MODE-set command.
*/
- out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
- * Issue NORMAL OP command.
+ * Issue RFEN command.
*/
- out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(200); /* Overkill. Must wait > 200 bus cycles */
#endif /* enable SDRAM init */
@@ -216,50 +251,6 @@ testdram(void)
}
#endif
-#if !defined(CONFIG_SPD_EEPROM)
-#define CONFIG_SYS_DDR_CONTROL 0xc300c000
-/*************************************************************************
- * fixed_sdram init -- doesn't use serial presence detect.
- * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
- out_be32(&ddr->cs0_bnds, 0x0000007f);
- out_be32(&ddr->cs1_bnds, 0x008000ff);
- out_be32(&ddr->cs2_bnds, 0x00000000);
- out_be32(&ddr->cs3_bnds, 0x00000000);
- out_be32(&ddr->cs0_config, 0x80010101);
- out_be32(&ddr->cs1_config, 0x80010101);
- out_be32(&ddr->cs2_config, 0x00000000);
- out_be32(&ddr->cs3_config, 0x00000000);
- out_be32(&ddr->timing_cfg_3, 0x00000000);
- out_be32(&ddr->timing_cfg_0, 0x00220802);
- out_be32(&ddr->timing_cfg_1, 0x38377322);
- out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
- out_be32(&ddr->sdram_cfg, 0x4300C000);
- out_be32(&ddr->sdram_cfg_2, 0x24401000);
- out_be32(&ddr->sdram_mode, 0x23C00542);
- out_be32(&ddr->sdram_mode_2, 0x00000000);
- out_be32(&ddr->sdram_interval, 0x05080100);
- out_be32(&ddr->sdram_md_cntl, 0x00000000);
- out_be32(&ddr->sdram_data_init, 0x00000000);
- out_be32(&ddr->sdram_clk_cntl, 0x03800000);
- asm("sync;isync;msync");
- udelay(500);
-
- #if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
- #else
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
- #endif
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
-
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI1 */
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index bb4c052..af927f1 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -46,12 +46,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 0: 64M Non-cacheable, guarded
- * 0xfc000000 56M 8MB -> 64MB of user flash
+ * 0xfc000000 56M unused
* 0xff800000 8M boot FLASH
+ * .... or ....
+ * 0xfc000000 64M user flash
+ *
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
- CONFIG_SYS_ALT_FLASH + 0x800000,
+ SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
@@ -74,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/*
* TLB 3: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
@@ -90,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
/*
* TLB 5: 16M Cacheable, non-guarded
@@ -102,9 +106,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_16M, 1),
+#ifndef CONFIG_SYS_ALT_BOOT
+ /*
+ * TLB 6: 64M Non-cacheable, guarded
+ * 0xec000000 64M 64MB user FLASH
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+#else
/*
* TLB 6: 4M Non-cacheable, guarded
- * 0xfb800000 4M 1st 4MB block of 64MB user FLASH
+ * 0xef800000 4M 1st 1/2 8MB soldered FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -112,12 +125,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 7: 4M Non-cacheable, guarded
- * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH
+ * 0xefc00000 4M 2nd half 8MB soldered FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
CONFIG_SYS_ALT_FLASH + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
};
generated by cgit v1.1 at 2024-11-09 07:54:32 +0000