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-rw-r--r--board/rpxsuper/flash.c18
-rw-r--r--board/rpxsuper/mii_phy.c4
-rw-r--r--board/rpxsuper/rpxsuper.c36
3 files changed, 29 insertions, 29 deletions
diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c
index 5f444bf..be29b65 100644
--- a/board/rpxsuper/flash.c
+++ b/board/rpxsuper/flash.c
@@ -33,7 +33,7 @@
#include <mpc8xx.h>
#include <asm/io.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
#define RD_SWP32(x) in_le32((volatile u32*)x)
@@ -53,21 +53,21 @@ unsigned long flash_init (void)
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* for now, only support the 4 MB Flash SIMM */
- size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]);
+ size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
/*
* protect monitor and environment sectors
*/
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@@ -81,7 +81,7 @@ unsigned long flash_init (void)
&flash_info[0]);
#endif
- return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024);
+ return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);
}
/*-----------------------------------------------------------------------
@@ -292,7 +292,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
addr = (vu_long*)(info->start[l_sect]);
while ( (addr[0] & 0x80808080) != 0x80808080 ||
(addr[1] & 0x80808080) != 0x80808080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -423,7 +423,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c
index ef99aff..12e23f4 100644
--- a/board/rpxsuper/mii_phy.c
+++ b/board/rpxsuper/mii_phy.c
@@ -54,7 +54,7 @@ mii_phy_read(unsigned short reg)
{
int i;
unsigned short tmp, val = 0, adr = 0;
- t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+ t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
tmp = 0x6002 | (adr << 7) | (reg << 2);
regs->bcsr4 = 0xC3;
@@ -83,7 +83,7 @@ mii_phy_write(unsigned short reg, unsigned short val)
{
int i;
unsigned short tmp, adr = 0;
- t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+ t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
tmp = 0x5002 | (adr << 7) | (reg << 2);
regs->bcsr4 = 0xC3;
diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c
index f633c5c..aa59803 100644
--- a/board/rpxsuper/rpxsuper.c
+++ b/board/rpxsuper/rpxsuper.c
@@ -193,11 +193,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
*/
int board_early_init_f (void)
{
- volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
- memctl->memc_br4 = CFG_BR4_PRELIM;
- memctl->memc_or4 = CFG_OR4_PRELIM;
+ memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+ memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */
regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */
return 0;
@@ -206,7 +206,7 @@ int board_early_init_f (void)
void
reset_phy(void)
{
- volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+ volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
regs->bcsr4 = 0xC3;
}
@@ -216,7 +216,7 @@ reset_phy(void)
int checkboard(void)
{
- volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+ volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
printf ("Board: Embedded Planet RPX Super, Revision %d\n",
regs->bcsr0 >> 4);
@@ -227,15 +227,15 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0, *ramaddr;
ulong psdmr, lsdmr, bcr;
long size = 0;
int i;
- psdmr = CFG_PSDMR;
- lsdmr = CFG_LSDMR;
+ psdmr = CONFIG_SYS_PSDMR;
+ lsdmr = CONFIG_SYS_LSDMR;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
@@ -254,17 +254,17 @@ phys_size_t initdram(int board_type)
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
- size = CFG_SDRAM0_SIZE;
+ size = CONFIG_SYS_SDRAM0_SIZE;
bcr = immap->im_siu_conf.sc_bcr;
immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM);
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- ramaddr = (uchar *)(CFG_SDRAM0_BASE);
- memctl->memc_psrt = CFG_PSRT;
+ ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE);
+ memctl->memc_psrt = CONFIG_SYS_PSRT;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
*ramaddr = c;
@@ -281,10 +281,10 @@ phys_size_t initdram(int board_type)
immap->im_siu_conf.sc_bcr = bcr;
-#ifndef CFG_RAMBOOT
-/* size += CFG_SDRAM1_SIZE; */
- ramaddr = (uchar *)(CFG_SDRAM1_BASE);
- memctl->memc_lsrt = CFG_LSRT;
+#ifndef CONFIG_SYS_RAMBOOT
+/* size += CONFIG_SYS_SDRAM1_SIZE; */
+ ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE);
+ memctl->memc_lsrt = CONFIG_SYS_LSRT;
memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
*ramaddr = c;
generated by cgit v1.1 at 2024-11-16 14:10:55 +0000