summaryrefslogtreecommitdiff
path: root/board/renesas
diff options
context:
space:
mode:
Diffstat (limited to 'board/renesas')
-rw-r--r--board/renesas/r2dplus/Makefile47
-rw-r--r--board/renesas/r2dplus/config.mk23
-rw-r--r--board/renesas/r2dplus/lowlevel_init.S154
-rw-r--r--board/renesas/r2dplus/r2dplus.c84
-rw-r--r--board/renesas/r2dplus/u-boot.lds105
5 files changed, 413 insertions, 0 deletions
diff --git a/board/renesas/r2dplus/Makefile b/board/renesas/r2dplus/Makefile
new file mode 100644
index 0000000..e96a8aa
--- /dev/null
+++ b/board/renesas/r2dplus/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := r2dplus.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/renesas/r2dplus/config.mk b/board/renesas/r2dplus/config.mk
new file mode 100644
index 0000000..1ec7dcc
--- /dev/null
+++ b/board/renesas/r2dplus/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x0FFC0000
diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S
new file mode 100644
index 0000000..5755de8
--- /dev/null
+++ b/board/renesas/r2dplus/lowlevel_init.S
@@ -0,0 +1,154 @@
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+ .global lowlevel_init
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_D, r0
+ mov.l r0,@r1
+
+ mov.l MMUCR_A,r1
+ mov.l MMUCR_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR1_A,r1
+ mov.l BCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l BCR2_A,r1
+ mov.l BCR2_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR3_A,r1
+ mov.l BCR3_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR4_A,r1
+ mov.l BCR4_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR1_A,r1
+ mov.l WCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR2_A,r1
+ mov.l WCR2_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR3_A,r1
+ mov.l WCR3_D,r0
+ mov.l r0,@r1
+
+ mov.l PCR_A,r1
+ mov.l PCR_D,r0
+ mov.w r0,@r1
+
+ mov.l LED_A,r1
+ mov #0xff,r0
+ mov.w r0,@r1
+
+ mov.l MCR_A,r1
+ mov.l MCR_D1,r0
+ mov.l r0,@r1
+
+ mov.l RTCNT_A,r1
+ mov.l RTCNT_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCOR_A,r1
+ mov.l RTCOR_D,r0
+ mov.w r0,@r1
+
+ mov.l RFCR_A,r1
+ mov.l RFCR_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCSR_A,r1
+ mov.l RTCSR_D,r0
+ mov.w r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0x55,r0
+ mov.b r0,@r1
+
+ /* Wait DRAM refresh 30 times */
+ mov.l RFCR_A,r1
+ mov #30,r3
+1:
+ mov.w @r1,r0
+ extu.w r0,r2
+ cmp/hi r3,r2
+ bf 1b
+
+ mov.l MCR_A,r1
+ mov.l MCR_D2,r0
+ mov.l r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0,r0
+ mov.b r0,@r1
+
+ mov.l IRLMASK_A,r1
+ mov.l IRLMASK_D,r0
+ mov.l r0,@r1
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_E, r0
+ mov.l r0, @r1
+
+ rts
+ nop
+
+ .align 2
+CCR_A: .long CCR /* Cache Control Register */
+CCR_D_D: .long 0x0808 /* Flush the cache, disable */
+CCR_D_E: .long 0x8000090B
+
+FRQCR_A: .long FRQCR /* FRQCR Address */
+FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
+BCR1_A: .long BCR1 /* BCR1 Address */
+BCR1_D: .long 0x00180008
+BCR2_A: .long BCR2 /* BCR2 Address */
+BCR2_D: .long 0xabe8
+BCR3_A: .long BCR3 /* BCR3 Address */
+BCR3_D: .long 0x0000
+BCR4_A: .long BCR4 /* BCR4 Address */
+BCR4_D: .long 0x00000010
+WCR1_A: .long WCR1 /* WCR1 Address */
+WCR1_D: .long 0x33343333
+WCR2_A: .long WCR2 /* WCR2 Address */
+WCR2_D: .long 0xcff86fbf
+WCR3_A: .long WCR3 /* WCR3 Address */
+WCR3_D: .long 0x07777707
+LED_A: .long 0x04000036 /* LED Address */
+RTCNT_A: .long RTCNT /* RTCNT Address */
+RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
+RTCOR_A: .long RTCOR /* RTCOR Address */
+RTCOR_D: .long 0xA534 /* RTCOR Write Code */
+RTCSR_A: .long RTCSR /* RTCSR Address */
+RTCSR_D: .long 0xA510 /* RTCSR Write Code */
+SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
+SDMR3_D: .long 0x55
+MCR_A: .long MCR /* MCR Address */
+MCR_D1: .long 0x081901F4 /* MRSET:'0' */
+MCR_D2: .long 0x481901F4 /* MRSET:'1' */
+RFCR_A: .long RFCR /* RFCR Address */
+RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
+PCR_A: .long PCR /* PCR Address */
+PCR_D: .long 0x0000
+MMUCR_A: .long MMUCR /* MMUCCR Address */
+MMUCR_D: .long 0x00000000 /* MMUCCR Data */
+IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
+IRLMASK_D: .long 0x00000000 /* IRLMASK Data */
diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c
new file mode 100644
index 0000000..0c08d68
--- /dev/null
+++ b/board/renesas/r2dplus/r2dplus.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Solutions R2D Plus\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#define FPGA_BASE 0xA4000000
+#define FPGA_CFCTL (FPGA_BASE + 0x04)
+#define CFCTL_EN (0x432)
+#define FPGA_CFPOW (FPGA_BASE + 0x06)
+#define CFPOW_ON (0x02)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN (0x01)
+
+void ide_set_reset(int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset) {
+ outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
+ outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+ outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
+ }
+}
+
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7751_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/renesas/r2dplus/u-boot.lds b/board/renesas/r2dplus/u-boot.lds
new file mode 100644
index 0000000..040e530
--- /dev/null
+++ b/board/renesas/r2dplus/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x0C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}