diff options
Diffstat (limited to 'board/renesas/alt/alt.c')
| -rw-r--r-- | board/renesas/alt/alt.c | 55 |
1 files changed, 54 insertions, 1 deletions
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index c0caeb9..f0010db 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -19,6 +19,7 @@ #include <asm/arch/rmobile.h> #include <asm/arch/rcar-mstp.h> #include <asm/arch/mmc.h> +#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> @@ -46,6 +47,11 @@ void s_init(void) #define ETHER_MSTP813 (1 << 13) #define IIC1_MSTP323 (1 << 23) #define MMC0_MSTP315 (1 << 15) +#define SDHI0_MSTP314 (1 << 14) +#define SDHI1_MSTP312 (1 << 12) + +#define SD1CKCR 0xE6150078 +#define SD1_97500KHZ 0x7 int board_early_init_f(void) { @@ -65,6 +71,17 @@ int board_early_init_f(void) /* MMC */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); #endif + +#ifdef CONFIG_SH_SDHI + /* SDHI0, 1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD1 to the 97.5MHz as well. + */ + writel(SD1_97500KHZ, SD1CKCR); +#endif return 0; } @@ -130,7 +147,7 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { - int ret = 0; + int ret = -ENODEV; #ifdef CONFIG_SH_MMCIF gpio_request(GPIO_GP_4_31, NULL); @@ -138,6 +155,42 @@ int board_mmc_init(bd_t *bis) ret = mmcif_mmc_init(); #endif + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DATA0, NULL); + gpio_request(GPIO_FN_SD0_DATA1, NULL); + gpio_request(GPIO_FN_SD0_DATA2, NULL); + gpio_request(GPIO_FN_SD0_DATA3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD1_DATA0, NULL); + gpio_request(GPIO_FN_SD1_DATA1, NULL); + gpio_request(GPIO_FN_SD1_DATA2, NULL); + gpio_request(GPIO_FN_SD1_DATA3, NULL); + gpio_request(GPIO_FN_SD1_CLK, NULL); + gpio_request(GPIO_FN_SD1_CMD, NULL); + gpio_request(GPIO_FN_SD1_CD, NULL); + + /* SDHI 0 */ + gpio_request(GPIO_GP_2_26, NULL); + gpio_request(GPIO_GP_2_29, NULL); + gpio_direction_output(GPIO_GP_2_26, 1); + gpio_direction_output(GPIO_GP_2_29, 1); + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 1 */ + gpio_request(GPIO_GP_4_26, NULL); + gpio_request(GPIO_GP_4_29, NULL); + gpio_direction_output(GPIO_GP_4_26, 1); + gpio_direction_output(GPIO_GP_4_29, 1); + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); +#endif return ret; } |