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-rw-r--r--board/purple/flash.c28
-rw-r--r--board/purple/purple.c24
-rw-r--r--board/purple/sconsole.c2
-rw-r--r--board/purple/sconsole.h2
-rw-r--r--board/purple/u-boot.lds4
5 files changed, 34 insertions, 26 deletions
diff --git a/board/purple/flash.c b/board/purple/flash.c
index 1baae35..37c7bec 100644
--- a/board/purple/flash.c
+++ b/board/purple/flash.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/inca-ip.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
typedef unsigned long FLASH_PORT_WIDTH;
typedef volatile unsigned long FLASH_PORT_WIDTHV;
@@ -207,7 +207,7 @@ unsigned long flash_init (void)
load_cmd(IN_RAM_CMD_READ);
/* Init: no FLASHes known */
- for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
ulong flashbase = PHYS_FLASH_1;
ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
@@ -229,20 +229,20 @@ unsigned long flash_init (void)
size += flash_info[i].size;
}
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CFG_MONITOR_BASE));
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SIZE-1,
- flash_get_info(CFG_ENV_ADDR));
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+ flash_get_info(CONFIG_ENV_ADDR));
#endif
return size;
@@ -282,13 +282,13 @@ static flash_info_t *flash_get_info(ulong base)
int i;
flash_info_t * info;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->start[0] <= base && base < info->start[0] + info->size)
break;
}
- return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
}
/*-----------------------------------------------------------------------
@@ -507,10 +507,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
start = get_timer(0);
- while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) {
+ while ((now = get_timer(start)) <= CONFIG_SYS_FLASH_ERASE_TOUT) {
/* show that we're waiting */
- if ((get_timer(last)) > CFG_HZ) {/* every second */
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
putc ('.');
last = get_timer(0);
}
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 9775591..54bef65 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/inca-ip.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
@@ -128,14 +129,14 @@ phys_size_t initdram(int board_type)
{
/* The only supported number of SDRAM banks is 4.
*/
-#define CFG_NB 4
+#define CONFIG_SYS_NB 4
ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW;
int cols = cfgpb0 & 0xF;
int rows = (cfgpb0 & 0xF0) >> 4;
int dw = cfgdw & 0xF;
- ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+ ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB;
void (* sdram_init) (ulong);
sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
@@ -252,25 +253,32 @@ void copy_code (ulong dest_addr)
/* copy u-boot code
*/
- copyLongs((ulong *)CFG_MONITOR_BASE,
+ copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE,
(ulong *)dest_addr,
- ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4);
+ ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4);
/* flush caches
*/
start = CKSEG0;
- end = start + CFG_DCACHE_SIZE;
+ end = start + CONFIG_SYS_DCACHE_SIZE;
while(start < end) {
cache_unroll(start,Index_Writeback_Inv_D);
- start += CFG_CACHELINE_SIZE;
+ start += CONFIG_SYS_CACHELINE_SIZE;
}
start = CKSEG0;
- end = start + CFG_ICACHE_SIZE;
+ end = start + CONFIG_SYS_ICACHE_SIZE;
while(start < end) {
cache_unroll(start,Index_Invalidate_I);
- start += CFG_CACHELINE_SIZE;
+ start += CONFIG_SYS_CACHELINE_SIZE;
}
}
+
+#ifdef CONFIG_PLB2800_ETHER
+int board_eth_init(bd_t *bis)
+{
+ return plb2800_eth_initialize(bis);
+}
+#endif
diff --git a/board/purple/sconsole.c b/board/purple/sconsole.c
index f52d50d..cd9d871 100644
--- a/board/purple/sconsole.c
+++ b/board/purple/sconsole.c
@@ -38,7 +38,7 @@ int serial_init (void)
sb->pos = 0;
sb->size = 0;
- sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
+ sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
return (0);
}
diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h
index e130ad4..baed5fb 100644
--- a/board/purple/sconsole.h
+++ b/board/purple/sconsole.h
@@ -33,7 +33,7 @@ typedef struct sconsole_buffer_s {
char data[1];
} sconsole_buffer_t;
-#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
+#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR)
extern void (* sconsole_putc) (char);
extern void (* sconsole_puts) (const char *);
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
index 972e6e7..bf1394b 100644
--- a/board/purple/u-boot.lds
+++ b/board/purple/u-boot.lds
@@ -42,7 +42,7 @@ SECTIONS
common/cmd_boot.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.ppcenv)
+ common/env_embedded.o (.ppcenv)
*(.text)
}
@@ -75,6 +75,6 @@ SECTIONS
. = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}
generated by cgit v1.1 at 2024-12-29 18:13:55 +0000