diff options
Diffstat (limited to 'board/purple/purple.c')
| -rw-r--r-- | board/purple/purple.c | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/board/purple/purple.c b/board/purple/purple.c index 9775591..54bef65 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> +#include <netdev.h> #include <asm/inca-ip.h> #include <asm/regdef.h> #include <asm/mipsregs.h> @@ -128,14 +129,14 @@ phys_size_t initdram(int board_type) { /* The only supported number of SDRAM banks is 4. */ -#define CFG_NB 4 +#define CONFIG_SYS_NB 4 ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW; int cols = cfgpb0 & 0xF; int rows = (cfgpb0 & 0xF0) >> 4; int dw = cfgdw & 0xF; - ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; + ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB; void (* sdram_init) (ulong); sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init); @@ -252,25 +253,32 @@ void copy_code (ulong dest_addr) /* copy u-boot code */ - copyLongs((ulong *)CFG_MONITOR_BASE, + copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE, (ulong *)dest_addr, - ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4); + ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4); /* flush caches */ start = CKSEG0; - end = start + CFG_DCACHE_SIZE; + end = start + CONFIG_SYS_DCACHE_SIZE; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); - start += CFG_CACHELINE_SIZE; + start += CONFIG_SYS_CACHELINE_SIZE; } start = CKSEG0; - end = start + CFG_ICACHE_SIZE; + end = start + CONFIG_SYS_ICACHE_SIZE; while(start < end) { cache_unroll(start,Index_Invalidate_I); - start += CFG_CACHELINE_SIZE; + start += CONFIG_SYS_CACHELINE_SIZE; } } + +#ifdef CONFIG_PLB2800_ETHER +int board_eth_init(bd_t *bis) +{ + return plb2800_eth_initialize(bis); +} +#endif |