diff options
Diffstat (limited to 'board/nvidia/common')
-rw-r--r-- | board/nvidia/common/board.c | 243 | ||||
-rw-r--r-- | board/nvidia/common/board.h | 4 |
2 files changed, 66 insertions, 181 deletions
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 160dac8..d13537d 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -43,24 +43,6 @@ const struct tegra2_sysinfo sysinfo = { CONFIG_TEGRA2_BOARD_STRING }; -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - /* Initialize periph clocks */ - clock_init(); - - /* Initialize periph pinmuxes */ - pinmux_init(); - - /* Initialize periph GPIOs */ - gpio_init(); - - /* Init UART, scratch regs, and start CPU */ - tegra2_start(); - return 0; -} -#endif /* EARLY_INIT */ - /* * Routine: timer_init * Description: init the timestamp and lastinc value @@ -70,62 +52,31 @@ int timer_init(void) return 0; } -/* - * Routine: clock_init_uart - * Description: init the PLL and clock for the UART(s) - */ -static void clock_init_uart(void) +static void enable_uart(enum periph_id pid) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH]; - u32 reg; - - reg = readl(&pll->pll_base); - if (!(reg & PLL_BASE_OVRRIDE_MASK)) { - /* Override pllp setup for 216MHz operation. */ - reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK | - (1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT); - reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT; - writel(reg, &pll->pll_base); - - reg |= PLL_ENABLE_MASK; - writel(reg, &pll->pll_base); - - reg &= ~PLL_BYPASS_MASK; - writel(reg, &pll->pll_base); - } - -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) /* Assert UART reset and enable clock */ - reset_set_enable(PERIPH_ID_UART1, 1); - clock_enable(PERIPH_ID_UART1); - - /* Enable pllp_out0 to UART */ - reg = readl(&clkrst->crc_clk_src_uarta); - reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */ - writel(reg, &clkrst->crc_clk_src_uarta); + reset_set_enable(pid, 1); + clock_enable(pid); + clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ /* wait for 2us */ udelay(2); /* De-assert reset to UART */ - reset_set_enable(PERIPH_ID_UART1, 0); + reset_set_enable(pid, 0); +} + +/* + * Routine: clock_init_uart + * Description: init the PLL and clock for the UART(s) + */ +static void clock_init_uart(void) +{ +#if defined(CONFIG_TEGRA2_ENABLE_UARTA) + enable_uart(PERIPH_ID_UART1); #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #if defined(CONFIG_TEGRA2_ENABLE_UARTD) - /* Assert UART reset and enable clock */ - reset_set_enable(PERIPH_ID_UART4, 1); - clock_enable(PERIPH_ID_UART4); - - /* Enable pllp_out0 to UART */ - reg = readl(&clkrst->crc_clk_src_uartd); - reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */ - writel(reg, &clkrst->crc_clk_src_uartd); - - /* wait for 2us */ - udelay(2); - - /* De-assert reset to UART */ - reset_set_enable(PERIPH_ID_UART4, 0); + enable_uart(PERIPH_ID_UART4); #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ } @@ -135,66 +86,29 @@ static void clock_init_uart(void) */ static void pin_mux_uart(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 reg; - #if defined(CONFIG_TEGRA2_ENABLE_UARTA) - reg = readl(&pmt->pmt_ctl_c); - reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */ - writel(reg, &pmt->pmt_ctl_c); + pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); + pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PIN_IRRX); - pinmux_tristate_disable(PIN_IRTX); + pinmux_tristate_disable(PINGRP_IRRX); + pinmux_tristate_disable(PINGRP_IRTX); #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #if defined(CONFIG_TEGRA2_ENABLE_UARTD) - reg = readl(&pmt->pmt_ctl_b); - reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */ - writel(reg, &pmt->pmt_ctl_b); + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); - pinmux_tristate_disable(PIN_GMC); + pinmux_tristate_disable(PINGRP_GMC); #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ } +#ifdef CONFIG_TEGRA2_MMC /* * Routine: clock_init_mmc * Description: init the PLL and clocks for the SDMMC controllers */ static void clock_init_mmc(void) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - u32 reg; - - /* Do the SDMMC resets/clock enables */ - reset_set_enable(PERIPH_ID_SDMMC4, 1); - clock_enable(PERIPH_ID_SDMMC4); - - /* Enable pllp_out0 to SDMMC4 */ - reg = readl(&clkrst->crc_clk_src_sdmmc4); - reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */ - reg |= (10 << 1); /* n-1, 11-1 shl 1 */ - writel(reg, &clkrst->crc_clk_src_sdmmc4); - - /* - * As per the Tegra2 TRM, section 5.3.4: - * 'Wait 2 us for the clock to flush through the pipe/logic' - */ - udelay(2); - - reset_set_enable(PERIPH_ID_SDMMC4, 1); - - reset_set_enable(PERIPH_ID_SDMMC3, 1); - clock_enable(PERIPH_ID_SDMMC3); - - /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */ - reg = readl(&clkrst->crc_clk_src_sdmmc3); - reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */ - reg |= (10 << 1); /* n-1, 11-1 shl 1 */ - writel(reg, &clkrst->crc_clk_src_sdmmc3); - - /* wait for 2us */ - udelay(2); - - reset_set_enable(PERIPH_ID_SDMMC3, 0); + clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000); + clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000); } /* @@ -203,65 +117,25 @@ static void clock_init_mmc(void) */ static void pin_mux_mmc(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 reg; - - /* SDMMC4 */ - /* config 2, x8 on 2nd set of pins */ - reg = readl(&pmt->pmt_ctl_a); - reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */ - writel(reg, &pmt->pmt_ctl_a); - reg = readl(&pmt->pmt_ctl_b); - reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */ - writel(reg, &pmt->pmt_ctl_b); - reg = readl(&pmt->pmt_ctl_d); - reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */ - writel(reg, &pmt->pmt_ctl_d); - - pinmux_tristate_disable(PIN_ATB); - pinmux_tristate_disable(PIN_GMA); - pinmux_tristate_disable(PIN_GME); - - /* SDMMC3 */ - /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ - reg = readl(&pmt->pmt_ctl_d); - reg &= 0xFFFF03FF; - reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */ - reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */ - reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */ - writel(reg, &pmt->pmt_ctl_d); - - pinmux_tristate_disable(PIN_SDC); - pinmux_tristate_disable(PIN_SDD); - pinmux_tristate_disable(PIN_SDB); -} - -/* - * Routine: clock_init - * Description: Do individual peripheral clock reset/enables - */ -void clock_init(void) -{ - clock_init_uart(); -} - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pin_mux_uart(); -} - -/* - * Routine: gpio_init - * Description: Do individual peripheral GPIO configs - */ -void gpio_init(void) -{ - gpio_config_uart(); + /* SDMMC4: config 3, x8 on 2nd set of pins */ + pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); + pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); + pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); + + pinmux_tristate_disable(PINGRP_ATB); + pinmux_tristate_disable(PINGRP_GMA); + pinmux_tristate_disable(PINGRP_GME); + + /* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ + pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3); + pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3); + pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3); + + pinmux_tristate_disable(PINGRP_SDC); + pinmux_tristate_disable(PINGRP_SDD); + pinmux_tristate_disable(PINGRP_SDB); } +#endif /* * Routine: board_init @@ -269,6 +143,9 @@ void gpio_init(void) */ int board_init(void) { + clock_init(); + clock_verify(); + /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); @@ -283,6 +160,7 @@ int board_mmc_init(bd_t *bd) /* Enable clocks, muxes, etc. for SDMMC controllers */ clock_init_mmc(); pin_mux_mmc(); + gpio_config_mmc(); debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 4-bit bus */ @@ -294,16 +172,25 @@ int board_mmc_init(bd_t *bd) return 0; } +#endif -/* this is a weak define that we are overriding */ -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) { - debug("board_mmc_getcd called\n"); - /* - * Hard-code CD presence for now. Need to add GPIO inputs - * for Seaboard & Harmony (& Kaen/Aebl/Wario?) - */ - *cd = 1; + /* Initialize essential common plls */ + clock_early_init(); + + /* Initialize UART clocks */ + clock_init_uart(); + + /* Initialize periph pinmuxes */ + pin_mux_uart(); + + /* Initialize periph GPIOs */ + gpio_config_uart(); + + /* Init UART, scratch regs, and start CPU */ + tegra2_start(); return 0; } -#endif +#endif /* EARLY_INIT */ diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index 4334c02..344e702 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -25,10 +25,8 @@ #define _BOARD_H_ void tegra2_start(void); -void clock_init(void); -void pinmux_init(void); -void gpio_init(void); void gpio_config_uart(void); +void gpio_config_mmc(void); int tegra2_mmc_init(int dev_index, int bus_width); #endif /* BOARD_H */ |