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-rw-r--r--board/netvia/flash.c30
-rw-r--r--board/netvia/netvia.c18
-rw-r--r--board/netvia/u-boot.lds3
-rw-r--r--board/netvia/u-boot.lds.debug2
4 files changed, 27 insertions, 26 deletions
diff --git a/board/netvia/flash.c b/board/netvia/flash.c
index d31f770..98479a5 100644
--- a/board/netvia/flash.c
+++ b/board/netvia/flash.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <mpc8xx.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@@ -38,13 +38,13 @@ static void flash_get_offsets(ulong base, flash_info_t * info);
unsigned long flash_init(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size;
int i;
/* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -54,28 +54,28 @@ unsigned long flash_init(void)
}
/* Remap FLASH according to real size */
- memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
/* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+ size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+ flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect ( FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
&flash_info[0]);
-#ifdef CFG_ENV_ADDR_REDUND
+#ifdef CONFIG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
&flash_info[0]);
#endif
@@ -427,7 +427,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
last = start;
addr = (vu_char *) (info->start[l_sect]);
while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return 1;
}
@@ -500,7 +500,7 @@ static int write_byte(flash_info_t * info, ulong dest, uchar data)
/* data polling for D7 */
start = get_timer(0);
while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c
index 4140bac..0b032c4 100644
--- a/board/netvia/netvia.c
+++ b/board/netvia/netvia.c
@@ -247,7 +247,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
@@ -256,17 +256,17 @@ phys_size_t initdram(int board_type)
/*
* Preliminary prescaler for refresh
*/
- memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
- memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */
+ memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */
udelay(200);
@@ -282,7 +282,7 @@ phys_size_t initdram(int board_type)
udelay(1000);
- memctl->memc_mamr = CFG_MAMR_9COL;
+ memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
size = SDRAM_MAX_SIZE;
@@ -358,7 +358,7 @@ int misc_init_r(void)
int board_early_init_f(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile iop8xx_t *ioport = &immap->im_ioport;
volatile cpm8xx_t *cpm = &immap->im_cpm;
volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -421,11 +421,11 @@ int board_early_init_f(void)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
- unsigned long totlen = nand_probe(CFG_NAND_BASE);
+ unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds
index b4f210e..6bc5768 100644
--- a/board/netvia/u-boot.lds
+++ b/board/netvia/u-boot.lds
@@ -63,7 +63,7 @@ SECTIONS
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ common/env_embedded.o (.text)
*(.text)
*(.fixup)
@@ -134,6 +134,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug
index 1014ec6..9210c43 100644
--- a/board/netvia/u-boot.lds.debug
+++ b/board/netvia/u-boot.lds.debug
@@ -61,7 +61,7 @@ SECTIONS
lib_generic/crc32.o (.text)
. = env_offset;
- common/environment.o(.text)
+ common/env_embedded.o(.text)
*(.text)
*(.fixup)
generated by cgit v1.1 at 2024-07-07 23:55:47 +0000