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-rw-r--r--board/mpl/common/flash.c2
-rw-r--r--board/mpl/common/memtst.c2
-rw-r--r--board/mpl/common/pci_parts.h2
-rw-r--r--board/mpl/mip405/mip405.c56
4 files changed, 46 insertions, 16 deletions
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index 28f6f0a..4bdb8bd 100644
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -105,6 +105,8 @@ unsigned long flash_init (void)
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
+ /* protect reset vector */
+ flash_info[0].protect[flash_info[0].sector_count-1] = 1;
size_b1 = 0 ;
flash_info[0].size = size_b0;
#if 0
diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
index c994a8b..2c77d37 100644
--- a/board/mpl/common/memtst.c
+++ b/board/mpl/common/memtst.c
@@ -494,7 +494,7 @@ void mem_test_reloc(void)
}
-int mem_test (unsigned long start, unsigned long ramsize, int quiet, int reloc)
+int mem_test (unsigned long start, unsigned long ramsize, int quiet)
{
unsigned long errors, stage;
unsigned long startaddr, size, i;
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
index 82426f3..e5627aa 100644
--- a/board/mpl/common/pci_parts.h
+++ b/board/mpl/common/pci_parts.h
@@ -110,7 +110,7 @@ static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
#if !defined(CONFIG_MIP405T)
{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
#else
- {PCI_CFG_PIIX4_IDETIM, 0x80000000, 4}, /* enable IDE channel0 */
+ {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
#endif
{ } /* end of device table */
};
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 07922bc..090041b 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -69,6 +69,7 @@
#include <miiphy.h>
#include "../common/common_util.h"
#include <i2c.h>
+#include <rtc.h>
extern block_dev_desc_t * scsi_get_dev(int dev);
extern block_dev_desc_t * ide_get_dev(int dev);
@@ -110,14 +111,14 @@ typedef struct {
} sdram_t;
#if defined(CONFIG_MIP405T)
const sdram_t sdram_table[] = {
- { 0x01, /* MIP405T Rev A, 64MByte -1 Board */
+ { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
3, /* Case Latenty = 3 */
3, /* trp 20ns / 7.5 ns datain[27] */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 (13x9x4) */
- 4, /* size value (64MByte) */
+ 2, /* Address Mode = 2 (12x9x4) */
+ 3, /* size value (32MByte) */
0}, /* ECC disabled */
{ 0xff, /* terminator */
0xff,
@@ -281,11 +282,6 @@ int init_sdram (void)
if((bc & 0x80)==0x80)
SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
#endif
-#if !defined(CONFIG_MIP405T)
- /* since the ECC initialisation needs some time,
- * we show that we're alive
- */
- serial_puts ("\nInitializing SDRAM, Please stand by");
/* set-up the chipselect machine */
mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
tmp = mfdcr (ebccfgd);
@@ -311,7 +307,6 @@ int init_sdram (void)
mtdcr (ebccfgd, UART1_AP);
mtdcr (ebccfga, pb3cr);
mtdcr (ebccfgd, UART1_CR);
-#endif
bc = in8 (PLD_BOARD_CFG_REG);
#ifdef SDRAM_DEBUG
serial_puts ("\nstart SDRAM Setup\n");
@@ -333,6 +328,11 @@ int init_sdram (void)
write_hex (i);
serial_puts (" \n");
#endif
+ /* since the ECC initialisation needs some time,
+ * we show that we're alive
+ */
+ if (sdram_table[i].ecc)
+ serial_puts ("\nInitializing SDRAM, Please stand by");
cal_val = sdram_table[i].cal - 1; /* Cas Latency */
trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
@@ -559,7 +559,7 @@ void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
unsigned char bc;
bc = in8 (PLD_BOARD_CFG_REG);
*pcbrev=(bc >> 4) & 0xf;
- *var=bc & 0xf ;
+ *var=16-(bc & 0xf);
#endif
}
@@ -654,8 +654,6 @@ long int initdram (int board_type)
/* ------------------------------------------------------------------------- */
-extern int mem_test (unsigned long start, unsigned long ramsize,
- int quiet);
static int test_dram (unsigned long ramsize)
{
@@ -666,8 +664,15 @@ static int test_dram (unsigned long ramsize)
return (1);
}
+/* used to check if the time in RTC is valid */
+static unsigned long start;
+static struct rtc_time tm;
+
int misc_init_r (void)
{
+ /* check, if RTC is running */
+ rtc_get (&tm);
+ start=get_timer(0);
/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
mtspr(ccr0, (mfspr(ccr0) & ~0x80));
@@ -688,9 +693,13 @@ void print_mip405_rev (void)
}
extern void mem_test_reloc(void);
+extern int mk_date (char *, struct rtc_time *);
int last_stage_init (void)
{
+ unsigned long stop;
+ struct rtc_time newtm;
+ unsigned char *s;
mem_test_reloc();
/* write correct LED configuration */
if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
@@ -704,6 +713,25 @@ int last_stage_init (void)
print_mip405_rev ();
show_stdio_dev ();
check_env ();
+ /* check if RTC time is valid */
+ stop=get_timer(start);
+ while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
+ udelay(1000);
+ stop=get_timer(start);
+ }
+ rtc_get (&newtm);
+ if(tm.tm_sec==newtm.tm_sec) {
+ s=getenv("defaultdate");
+ if(!s)
+ mk_date ("010112001970", &newtm);
+ else
+ if(mk_date (s, &newtm)!=0) {
+ printf("RTC: Bad date format in defaultdate\n");
+ return 0;
+ }
+ rtc_reset ();
+ rtc_set(&newtm);
+ }
return 0;
}
@@ -745,10 +773,10 @@ void print_mip405_info (void)
printf ("SER1 uses handshakes %s\n",
(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
#else
- printf ("User Config Switch %d %d %d %d %d %d %d %d %d\n",
+ printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
- (ext >> 6) & 0x1,(ext >> 7) & 0x1,(ext >> 8) & 0x1);
+ (ext >> 6) & 0x1,(ext >> 7) & 0x1);
#endif
printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
printf ("IRQs:\n");
generated by cgit v1.1 at 2024-11-26 02:23:55 +0000