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-rw-r--r--board/mpl/common/flash.c58
-rw-r--r--board/mpl/mip405/init.S74
-rw-r--r--board/mpl/mip405/mip405.c132
-rw-r--r--board/mpl/pip405/init.S74
-rw-r--r--board/mpl/pip405/pip405.c82
5 files changed, 210 insertions, 210 deletions
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index 355608c..682f0e7 100644
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -97,7 +97,7 @@ int get_boot_mode(void)
{
unsigned long pbcr;
int res = 0;
- pbcr = mfdcr (strap);
+ pbcr = mfdcr (CPC0_PSR);
if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
/* boot via MPS or MPS mapping */
res = BOOT_MPS;
@@ -123,29 +123,29 @@ void setup_cs_reloc(void)
/* first findout on which cs the flash is */
if(mode & BOOT_MPS) {
/* map flash high on CS1 and MPS on CS0 */
- mtdcr (ebccfga, pb0ap);
- mtdcr (ebccfgd, MPS_AP);
- mtdcr (ebccfga, pb0cr);
- mtdcr (ebccfgd, MPS_CR);
+ mtdcr (EBC0_CFGADDR, PB0AP);
+ mtdcr (EBC0_CFGDATA, MPS_AP);
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ mtdcr (EBC0_CFGDATA, MPS_CR);
/* we use the default values (max values) for the flash
* because its real size is not yet known */
- mtdcr (ebccfga, pb1ap);
- mtdcr (ebccfgd, FLASH_AP);
- mtdcr (ebccfga, pb1cr);
- mtdcr (ebccfgd, FLASH_CR_B);
+ mtdcr (EBC0_CFGADDR, PB1AP);
+ mtdcr (EBC0_CFGDATA, FLASH_AP);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, FLASH_CR_B);
}
else {
/* map flash high on CS0 and MPS on CS1 */
- mtdcr (ebccfga, pb1ap);
- mtdcr (ebccfgd, MPS_AP);
- mtdcr (ebccfga, pb1cr);
- mtdcr (ebccfgd, MPS_CR);
+ mtdcr (EBC0_CFGADDR, PB1AP);
+ mtdcr (EBC0_CFGDATA, MPS_AP);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, MPS_CR);
/* we use the default values (max values) for the flash
* because its real size is not yet known */
- mtdcr (ebccfga, pb0ap);
- mtdcr (ebccfgd, FLASH_AP);
- mtdcr (ebccfga, pb0cr);
- mtdcr (ebccfgd, FLASH_CR_B);
+ mtdcr (EBC0_CFGADDR, PB0AP);
+ mtdcr (EBC0_CFGDATA, FLASH_AP);
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ mtdcr (EBC0_CFGDATA, FLASH_CR_B);
}
}
@@ -217,34 +217,34 @@ unsigned long flash_init (void)
}
if(mode & BOOT_MPS) {
/* flash is on CS1 */
- mtdcr(ebccfga, pb1cr);
- flashcr = mfdcr (ebccfgd);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ flashcr = mfdcr (EBC0_CFGDATA);
/* we map the flash high in every case */
flashcr&=0x0001FFFF; /* mask out address bits */
flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
flashcr|= (i << 17); /* size addr */
- mtdcr(ebccfga, pb1cr);
- mtdcr(ebccfgd, flashcr);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ mtdcr(EBC0_CFGDATA, flashcr);
}
else {
/* flash is on CS0 */
- mtdcr(ebccfga, pb0cr);
- flashcr = mfdcr (ebccfgd);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ flashcr = mfdcr (EBC0_CFGDATA);
/* we map the flash high in every case */
flashcr&=0x0001FFFF; /* mask out address bits */
flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
flashcr|= (i << 17); /* size addr */
- mtdcr(ebccfga, pb0cr);
- mtdcr(ebccfgd, flashcr);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, flashcr);
}
#if 0
/* enable this (PIP405/MIP405 only) if you want to test if
the relocation has be done ok.
This will disable both Chipselects */
- mtdcr (ebccfga, pb0cr);
- mtdcr (ebccfgd, 0L);
- mtdcr (ebccfga, pb1cr);
- mtdcr (ebccfgd, 0L);
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ mtdcr (EBC0_CFGDATA, 0L);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, 0L);
printf("CS0 & CS1 switched off for test\n");
#endif
/* patch version_string */
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
index 19d9220..f3d94c3 100644
--- a/board/mpl/mip405/init.S
+++ b/board/mpl/mip405/init.S
@@ -55,7 +55,7 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
- mfdcr r3,strap /* get strapping reg */
+ mfdcr r3,CPC0_PSR /* get strapping reg */
andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
bnelr /* jump back if PCI boot */
@@ -84,9 +84,9 @@ ext_bus_cntlr_init:
/*-----------------------------------------------------------------------
* decide boot up mode
*----------------------------------------------------------------------- */
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- mfdcr r4,ebccfgd
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ mfdcr r4,EBC0_CFGDATA
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
beq 0f /* jump if 8 bit bus width */
@@ -96,18 +96,18 @@ ext_bus_cntlr_init:
* Memory Bank 0 (16 Bit Flash) initialization
*---------------------------------------------------------------------- */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
b 1f
0:
@@ -117,66 +117,66 @@ ext_bus_cntlr_init:
* Memory Bank 0 Multi Purpose Socket initialization
*----------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
1:
/*-----------------------------------------------------------------------
* Memory Bank 2-3-4-5-6 (not used) initialization
*-----------------------------------------------------------------------*/
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
+ addi r4,0,PB1CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
+ addi r4,0,PB2CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
+ addi r4,0,PB3CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
+ addi r4,0,PB4CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
+ addi r4,0,PB5CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb6cr
- mtdcr ebccfga,r4
+ addi r4,0,PB6CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb7cr
- mtdcr ebccfga,r4
+ addi r4,0,PB7CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
nop /* pass2 DCR errata #8 */
blr
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 1738f54..d8279e8 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -256,16 +256,16 @@ int init_sdram (void)
gd->baudrate = 9600;
serial_init ();
/* set up the pld */
- mtdcr (ebccfga, pb7ap);
- mtdcr (ebccfgd, PLD_AP);
- mtdcr (ebccfga, pb7cr);
- mtdcr (ebccfgd, PLD_CR);
+ mtdcr (EBC0_CFGADDR, PB7AP);
+ mtdcr (EBC0_CFGDATA, PLD_AP);
+ mtdcr (EBC0_CFGADDR, PB7CR);
+ mtdcr (EBC0_CFGDATA, PLD_CR);
/* THIS IS OBSOLETE */
/* set up the board rev reg*/
- mtdcr (ebccfga, pb5ap);
- mtdcr (ebccfgd, BOARD_AP);
- mtdcr (ebccfga, pb5cr);
- mtdcr (ebccfgd, BOARD_CR);
+ mtdcr (EBC0_CFGADDR, PB5AP);
+ mtdcr (EBC0_CFGDATA, BOARD_AP);
+ mtdcr (EBC0_CFGADDR, PB5CR);
+ mtdcr (EBC0_CFGDATA, BOARD_CR);
#ifdef SDRAM_DEBUG
/* get all informations from PLD */
serial_puts ("\nPLD Part 0x");
@@ -289,30 +289,30 @@ int init_sdram (void)
SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
#endif
/* set-up the chipselect machine */
- mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
- tmp = mfdcr (ebccfgd);
+ mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
+ tmp = mfdcr (EBC0_CFGDATA);
if ((tmp & 0x00002000) == 0) {
/* MPS Boot, set up the flash */
- mtdcr (ebccfga, pb1ap);
- mtdcr (ebccfgd, FLASH_AP);
- mtdcr (ebccfga, pb1cr);
- mtdcr (ebccfgd, FLASH_CR);
+ mtdcr (EBC0_CFGADDR, PB1AP);
+ mtdcr (EBC0_CFGDATA, FLASH_AP);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, FLASH_CR);
} else {
/* Flash boot, set up the MPS */
- mtdcr (ebccfga, pb1ap);
- mtdcr (ebccfgd, MPS_AP);
- mtdcr (ebccfga, pb1cr);
- mtdcr (ebccfgd, MPS_CR);
+ mtdcr (EBC0_CFGADDR, PB1AP);
+ mtdcr (EBC0_CFGDATA, MPS_AP);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, MPS_CR);
}
/* set up UART0 (CS2) and UART1 (CS3) */
- mtdcr (ebccfga, pb2ap);
- mtdcr (ebccfgd, UART0_AP);
- mtdcr (ebccfga, pb2cr);
- mtdcr (ebccfgd, UART0_CR);
- mtdcr (ebccfga, pb3ap);
- mtdcr (ebccfgd, UART1_AP);
- mtdcr (ebccfga, pb3cr);
- mtdcr (ebccfgd, UART1_CR);
+ mtdcr (EBC0_CFGADDR, PB2AP);
+ mtdcr (EBC0_CFGDATA, UART0_AP);
+ mtdcr (EBC0_CFGADDR, PB2CR);
+ mtdcr (EBC0_CFGDATA, UART0_CR);
+ mtdcr (EBC0_CFGADDR, PB3AP);
+ mtdcr (EBC0_CFGDATA, UART1_AP);
+ mtdcr (EBC0_CFGADDR, PB3CR);
+ mtdcr (EBC0_CFGDATA, UART1_CR);
bc = in8 (PLD_BOARD_CFG_REG);
#ifdef SDRAM_DEBUG
serial_puts ("\nstart SDRAM Setup\n");
@@ -348,8 +348,8 @@ int init_sdram (void)
/* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks;
/* get SDRAM timing register */
- mtdcr (memcfga, mem_sdtr1);
- sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
+ mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
sdram_tim |= ((unsigned long) (cal_val)) << 23;
/* insert PTA value */
@@ -369,8 +369,8 @@ int init_sdram (void)
/* insert SZ value; */
tmp |= ((unsigned long) sdram_table[i].sz << 17);
/* get SDRAM bank 0 register */
- mtdcr (memcfga, mem_mb0cf);
- sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
+ mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG
@@ -380,8 +380,8 @@ int init_sdram (void)
#endif
/* write SDRAM timing register */
- mtdcr (memcfga, mem_sdtr1);
- mtdcr (memcfgd, sdram_tim);
+ mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGDATA, sdram_tim);
#ifdef SDRAM_DEBUG
serial_puts ("mb0cf: ");
@@ -390,23 +390,23 @@ int init_sdram (void)
#endif
/* write SDRAM bank 0 register */
- mtdcr (memcfga, mem_mb0cf);
- mtdcr (memcfgd, sdram_bank);
+ mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGDATA, sdram_bank);
if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
/* get SDRAM refresh interval register */
- mtdcr (memcfga, mem_rtr);
- tmp = mfdcr (memcfgd) & ~0x3FF80000;
+ mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x07F00000;
} else {
/* get SDRAM refresh interval register */
- mtdcr (memcfga, mem_rtr);
- tmp = mfdcr (memcfgd) & ~0x3FF80000;
+ mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x05F00000;
}
/* write SDRAM refresh interval register */
- mtdcr (memcfga, mem_rtr);
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGDATA, tmp);
/* enable ECC if used */
#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
if (sdram_table[i].ecc) {
@@ -415,19 +415,19 @@ int init_sdram (void)
#ifdef SDRAM_DEBUG
serial_puts ("disable ECC.. ");
#endif
- mtdcr (memcfga, mem_ecccf);
- tmp = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff; /* disable all banks */
- mtdcr (memcfga, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, mem_ecccf);
/* set up SDRAM Controller with ECC enabled */
#ifdef SDRAM_DEBUG
serial_puts ("setup SDRAM Controller.. ");
#endif
- mtdcr (memcfgd, tmp);
- mtdcr (memcfga, mem_mcopt1);
- tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
- mtdcr (memcfga, mem_mcopt1);
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
+ mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
#ifdef SDRAM_DEBUG
serial_puts ("fill the memory..\n");
@@ -447,19 +447,19 @@ int init_sdram (void)
serial_puts ("enable ECC\n");
#endif
udelay (400);
- mtdcr (memcfga, mem_ecccf);
- tmp = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000; /* enable bank 0 */
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
} else
#endif
{
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (memcfga, mem_mcopt1);
- tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
- mtdcr (memcfga, mem_mcopt1);
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
+ mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
}
serial_puts ("\n");
@@ -631,14 +631,14 @@ phys_size_t initdram (int board_type)
ds = 0;
/* since the DRAM controller is allready set up, calculate the size with the
bank registers */
- mtdcr (memcfga, mem_mb0cf);
- bank_reg[0] = mfdcr (memcfgd);
- mtdcr (memcfga, mem_mb1cf);
- bank_reg[1] = mfdcr (memcfgd);
- mtdcr (memcfga, mem_mb2cf);
- bank_reg[2] = mfdcr (memcfgd);
- mtdcr (memcfga, mem_mb3cf);
- bank_reg[3] = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {
if ((bank_reg[i] & 0x1) == 0x1) {
@@ -648,8 +648,8 @@ phys_size_t initdram (int board_type)
} else
ds = 1;
}
- mtdcr (memcfga, mem_ecccf);
- tmp = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ tmp = mfdcr (SDRAM0_CFGDATA);
if (!tmp)
printf ("No ");
@@ -687,7 +687,7 @@ int misc_init_r (void)
rtc_get (&tm);
start=get_timer(0);
/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
- if (mfdcr(strap) & PSR_ROM_LOC)
+ if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
index 61f37d7..18e8b09 100644
--- a/board/mpl/pip405/init.S
+++ b/board/mpl/pip405/init.S
@@ -54,7 +54,7 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
- mfdcr r3,strap /* get strapping reg */
+ mfdcr r3,CPC0_PSR /* get strapping reg */
andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
bnelr /* jump back if PCI boot */
@@ -83,9 +83,9 @@
/*-----------------------------------------------------------------------
* decide boot up mode
*----------------------------------------------------------------------- */
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- mfdcr r4,ebccfgd
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ mfdcr r4,EBC0_CFGDATA
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
beq 0f /* jump if 8 bit bus width */
@@ -95,18 +95,18 @@
* Memory Bank 0 (16 Bit Flash) initialization
*---------------------------------------------------------------------- */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
b 1f
0:
@@ -115,65 +115,65 @@
* Memory Bank 0 Multi Purpose Socket initialization
*----------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
1:
/*-----------------------------------------------------------------------
* Memory Bank 2-3-4-5-6 (not used) initialization
*-----------------------------------------------------------------------*/
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
+ addi r4,0,PB1CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
+ addi r4,0,PB2CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
+ addi r4,0,PB3CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
+ addi r4,0,PB4CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
+ addi r4,0,PB5CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb6cr
- mtdcr ebccfga,r4
+ addi r4,0,PB6CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb7cr
- mtdcr ebccfga,r4
+ addi r4,0,PB7CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
nop /* pass2 DCR errata #8 */
blr
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index 677437d..e00d1d0 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -193,10 +193,10 @@ int board_early_init_f (void)
unsigned char cal_index, cal_val, spd_version, spd_chksum;
unsigned char buf[8];
/* set up the config port */
- mtdcr (ebccfga, pb7ap);
- mtdcr (ebccfgd, CONFIG_PORT_AP);
- mtdcr (ebccfga, pb7cr);
- mtdcr (ebccfgd, CONFIG_PORT_CR);
+ mtdcr (EBC0_CFGADDR, PB7AP);
+ mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
+ mtdcr (EBC0_CFGADDR, PB7CR);
+ mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
memclk = get_bus_freq (tmemclk);
tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
@@ -361,8 +361,8 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM");
/* get SDRAM timing register */
- mtdcr (memcfga, mem_sdtr1);
- tmp = mfdcr (memcfgd) & ~0x018FC01F;
+ mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
/* tmp |= ((unsigned long)cal_val) << 23; */
tmp |= ((unsigned long) cal_val) << 23;
@@ -385,8 +385,8 @@ int board_early_init_f (void)
#endif
/* write SDRAM timing register */
- mtdcr (memcfga, mem_sdtr1);
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGDATA, tmp);
baseaddr = CONFIG_SYS_SDRAM_BASE;
bank_size = (((unsigned long) density) << 22) / 2;
/* insert AM value */
@@ -418,8 +418,8 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM");
} /* endswitch */
/* get SDRAM bank 0 register */
- mtdcr (memcfga, mem_mb0cf);
- bank = mfdcr (memcfgd) & ~0xFFCEE001;
+ mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG
serial_puts ("bank0: baseaddr: ");
@@ -434,12 +434,12 @@ int board_early_init_f (void)
sdram_size += bank_size;
/* write SDRAM bank 0 register */
- mtdcr (memcfga, mem_mb0cf);
- mtdcr (memcfgd, bank);
+ mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 1 register */
- mtdcr (memcfga, mem_mb1cf);
- bank = mfdcr (memcfgd) & ~0xFFCEE001;
+ mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_size = 0;
#ifdef SDRAM_DEBUG
@@ -459,12 +459,12 @@ int board_early_init_f (void)
serial_puts ("\n");
#endif
/* write SDRAM bank 1 register */
- mtdcr (memcfga, mem_mb1cf);
- mtdcr (memcfgd, bank);
+ mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 2 register */
- mtdcr (memcfga, mem_mb2cf);
- bank = mfdcr (memcfgd) & ~0xFFCEE001;
+ mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
@@ -482,12 +482,12 @@ int board_early_init_f (void)
sdram_size += bank_size;
/* write SDRAM bank 2 register */
- mtdcr (memcfga, mem_mb2cf);
- mtdcr (memcfgd, bank);
+ mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 3 register */
- mtdcr (memcfga, mem_mb3cf);
- bank = mfdcr (memcfgd) & ~0xFFCEE001;
+ mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
#ifdef SDRAM_DEBUG
serial_puts ("bank3: baseaddr: ");
@@ -509,13 +509,13 @@ int board_early_init_f (void)
#endif
/* write SDRAM bank 3 register */
- mtdcr (memcfga, mem_mb3cf);
- mtdcr (memcfgd, bank);
+ mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM refresh interval register */
- mtdcr (memcfga, mem_rtr);
- tmp = mfdcr (memcfgd) & ~0x3FF80000;
+ mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
if (tmemclk < NSto10PS (16))
tmp |= 0x05F00000;
@@ -523,14 +523,14 @@ int board_early_init_f (void)
tmp |= 0x03F80000;
/* write SDRAM refresh interval register */
- mtdcr (memcfga, mem_rtr);
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGDATA, tmp);
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (memcfga, mem_mcopt1);
- tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
- mtdcr (memcfga, mem_mcopt1);
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
+ mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGDATA, tmp);
/*-------------------------------------------------------------------------+
@@ -619,14 +619,14 @@ phys_size_t initdram (int board_type)
/* since the DRAM controller is allready set up,
* calculate the size with the bank registers
*/
- mtdcr (memcfga, mem_mb0cf);
- bank_reg[0] = mfdcr (memcfgd);
- mtdcr (memcfga, mem_mb1cf);
- bank_reg[1] = mfdcr (memcfgd);
- mtdcr (memcfga, mem_mb2cf);
- bank_reg[2] = mfdcr (memcfgd);
- mtdcr (memcfga, mem_mb3cf);
- bank_reg[3] = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {
if ((bank_reg[i] & 0x1) == 0x1) {
@@ -668,7 +668,7 @@ int misc_init_r (void)
gd->bd->bi_flashoffset=0;
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
- if (mfdcr(strap) & PSR_ROM_LOC)
+ if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
generated by cgit v1.1 at 2024-11-10 21:06:02 +0000