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-rw-r--r--board/mpl/common/common_util.c14
-rw-r--r--board/mpl/common/common_util.h2
-rw-r--r--board/mpl/common/flash.c2
-rw-r--r--board/mpl/common/kbd.c256
-rw-r--r--board/mpl/common/memtst.c14
-rw-r--r--board/mpl/common/pci.c2
-rw-r--r--board/mpl/common/pci_parts.h36
-rw-r--r--board/mpl/common/usb_uhci.c2
-rw-r--r--board/mpl/mip405/cmd_mip405.c10
-rw-r--r--board/mpl/mip405/mip405.c12
-rw-r--r--board/mpl/mip405/mip405.h28
-rw-r--r--board/mpl/mip405/u-boot.lds8
-rw-r--r--board/mpl/pati/cmd_pati.c6
-rw-r--r--board/mpl/pati/pati.c2
-rw-r--r--board/mpl/pati/pati.h50
-rw-r--r--board/mpl/pati/pci_eeprom.h102
-rw-r--r--board/mpl/pip405/cmd_pip405.c10
-rw-r--r--board/mpl/pip405/pip405.h20
-rw-r--r--board/mpl/pip405/u-boot.lds8
-rw-r--r--board/mpl/pip405/u-boot.lds.debug8
-rw-r--r--board/mpl/vcma9/cmd_vcma9.c4
-rw-r--r--board/mpl/vcma9/lowlevel_init.S142
22 files changed, 368 insertions, 370 deletions
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 785d204..11d4345 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -219,7 +219,7 @@ mpl_prg_image(uchar *ld_addr)
uchar *buf;
/* reserve space for uncompressed image */
if ((buf = malloc(IMAGE_SIZE)) == NULL) {
- puts("Insufficient space for decompression\n");
+ puts("Insufficient space for decompression\n");
return 1;
}
@@ -461,7 +461,7 @@ void show_stdio_dev(void)
int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- ulong size,src,ld_addr;
+ ulong size,src,ld_addr;
int result;
#if !defined(CONFIG_PATI)
backup_t back;
@@ -473,11 +473,11 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_CMD_FDC)
if (strcmp(argv[2], "floppy") == 0) {
- char *local_args[3];
+ char *local_args[3];
extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
puts("\nupdating bootloader image from floppy\n");
local_args[0] = argv[0];
- if(argc==4) {
+ if(argc==4) {
local_args[1] = argv[3];
local_args[2] = NULL;
ld_addr=simple_strtoul(argv[3], NULL, 16);
@@ -493,7 +493,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#endif
if (strcmp(argv[2], "mem") == 0) {
- if(argc==4) {
+ if(argc==4) {
ld_addr=simple_strtoul(argv[3], NULL, 16);
}
else {
@@ -524,7 +524,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
src&=0xfff00000;
size=0;
do {
- size++;
+ size++;
printf("\n\nPass %ld\n",size);
mem_test(CFG_MEMTEST_START,src,1);
if(ctrlc())
@@ -538,7 +538,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#if !defined(CONFIG_PATI)
if (strcmp(argv[1], "clearenvvalues") == 0)
{
- if (strcmp(argv[2], "yes") == 0)
+ if (strcmp(argv[2], "yes") == 0)
{
clear_env_values();
return 0;
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
index d4b1f68..46573da 100644
--- a/board/mpl/common/common_util.h
+++ b/board/mpl/common/common_util.h
@@ -26,7 +26,7 @@
typedef struct {
char signature[4];
- char serial_name[17]; /* "MIP405_1000xxxxx" */
+ char serial_name[17]; /* "MIP405_1000xxxxx" */
char eth_addr[21]; /* "00:60:C2:0a:00:00" */
} backup_t;
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index 6f53192..a437dab 100644
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -398,7 +398,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
- /* printf("Device value %x\n",value); */
+ /* printf("Device value %x\n",value); */
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_F040B:
info->flash_id += FLASH_AM040;
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
index 7724e24..931ed43 100644
--- a/board/mpl/common/kbd.c
+++ b/board/mpl/common/kbd.c
@@ -53,63 +53,63 @@ void enable_8259A_irq(unsigned int irq);
#define KBD_STAT_KOBF 0x01
#define KBD_STAT_IBF 0x02
#define KBD_STAT_SYS 0x04
-#define KBD_STAT_CD 0x08
+#define KBD_STAT_CD 0x08
#define KBD_STAT_LOCK 0x10
#define KBD_STAT_MOBF 0x20
-#define KBD_STAT_TI_OUT 0x40
-#define KBD_STAT_PARERR 0x80
+#define KBD_STAT_TI_OUT 0x40
+#define KBD_STAT_PARERR 0x80
-#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
-#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
-#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */
+#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */
/*
* Keyboard Controller Commands
*/
-#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
-#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
-#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
+#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
+#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
+#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
-#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
-#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
+#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
+#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
+#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
+#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
/*
* Keyboard Commands
*/
-#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
-#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
-#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
-#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
-#define KBD_CMD_RESET 0xFF /* Reset */
+#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
+#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
+#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
+#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
+#define KBD_CMD_RESET 0xFF /* Reset */
/*
* Keyboard Replies
*/
-#define KBD_REPLY_POR 0xAA /* Power on reset */
-#define KBD_REPLY_ACK 0xFA /* Command ACK */
-#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
+#define KBD_REPLY_POR 0xAA /* Power on reset */
+#define KBD_REPLY_ACK 0xFA /* Command ACK */
+#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
/*
* Status Register Bits
*/
-#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
-#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
-#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
-#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
-#define KBD_STAT_PERR 0x80 /* Parity error */
+#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
+#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
+#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
+#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
+#define KBD_STAT_PERR 0x80 /* Parity error */
#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
@@ -117,24 +117,24 @@ void enable_8259A_irq(unsigned int irq);
* Controller Mode Register Bits
*/
-#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 0x04 /* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
+#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS 0x04 /* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
-#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
-#define KBD_MODE_RFU 0x80
+#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
+#define KBD_MODE_RFU 0x80
-#define KDB_DATA_PORT 0x60
+#define KDB_DATA_PORT 0x60
#define KDB_COMMAND_PORT 0x64
-#define LED_SCR 0x01 /* scroll lock led */
-#define LED_CAP 0x04 /* caps lock led */
-#define LED_NUM 0x02 /* num lock led */
+#define LED_SCR 0x01 /* scroll lock led */
+#define LED_CAP 0x04 /* caps lock led */
+#define LED_NUM 0x02 /* num lock led */
-#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
+#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
static volatile char kbd_buffer[KBD_BUFFER_LEN];
@@ -197,8 +197,7 @@ int isa_kbd_init(void)
irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
return (1);
- }
- else {
+ } else {
printf("%s\n",result);
return (-1);
}
@@ -216,20 +215,20 @@ int overwrite_console (void)
int drv_isa_kbd_init (void)
{
int error;
- device_t kbddev ;
+ device_t kbddev ;
char *stdinname = getenv ("stdin");
if(isa_kbd_init()==-1)
return -1;
- memset (&kbddev, 0, sizeof(kbddev));
- strcpy(kbddev.name, DEVNAME);
- kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- kbddev.putc = NULL ;
+ memset (&kbddev, 0, sizeof(kbddev));
+ strcpy(kbddev.name, DEVNAME);
+ kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ kbddev.putc = NULL ;
kbddev.puts = NULL ;
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
- error = device_register (&kbddev);
+ error = device_register (&kbddev);
if(error==0) {
/* check if this is the standard input device */
if(strcmp(stdinname,DEVNAME)==0) {
@@ -313,106 +312,106 @@ void kbd_set_leds(void)
}
-void handle_keyboard_event(unsigned char scancode)
+void handle_keyboard_event (unsigned char scancode)
{
unsigned char keycode;
/* Convert scancode to keycode */
- PRINTF("scancode %x\n",scancode);
- if(scancode==0xe0) {
- e0=1; /* special charakters */
+ PRINTF ("scancode %x\n", scancode);
+ if (scancode == 0xe0) {
+ e0 = 1; /* special charakters */
return;
}
- if(e0==1) {
- e0=0; /* delete flag */
- if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */
- ((scancode&0x7F)==0x1D)|| /* the right alt key */
- ((scancode&0x7F)==0x35)|| /* the right '/' key */
- ((scancode&0x7F)==0x1C) )) /* the right enter key */
+ if (e0 == 1) {
+ e0 = 0; /* delete flag */
+ if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
+ ((scancode & 0x7F) == 0x1D) || /* the right alt key */
+ ((scancode & 0x7F) == 0x35) || /* the right '/' key */
+ ((scancode & 0x7F) == 0x1C)))
+ /* the right enter key */
/* we swallow unknown e0 codes */
return;
}
/* special cntrl keys */
- switch(scancode)
- {
- case 0x2A:
- case 0x36: /* shift pressed */
- shift=1;
- return; /* do nothing else */
- case 0xAA:
- case 0xB6: /* shift released */
- shift=0;
- return; /* do nothing else */
- case 0x38: /* alt pressed */
- alt=1;
- return; /* do nothing else */
- case 0xB8: /* alt released */
- alt=0;
- return; /* do nothing else */
- case 0x1d: /* ctrl pressed */
- ctrl=1;
- return; /* do nothing else */
- case 0x9d: /* ctrl released */
- ctrl=0;
- return; /* do nothing else */
- case 0x46: /* scrollock pressed */
- scroll_lock=~scroll_lock;
- kbd_set_leds();
- return; /* do nothing else */
- case 0x3A: /* capslock pressed */
- caps_lock=~caps_lock;
- kbd_set_leds();
- return;
- case 0x45: /* numlock pressed */
- num_lock=~num_lock;
- kbd_set_leds();
- return;
- case 0xC6: /* scroll lock released */
- case 0xC5: /* num lock released */
- case 0xBA: /* caps lock released */
- return; /* just swallow */
+ switch (scancode) {
+ case 0x2A:
+ case 0x36: /* shift pressed */
+ shift = 1;
+ return; /* do nothing else */
+ case 0xAA:
+ case 0xB6: /* shift released */
+ shift = 0;
+ return; /* do nothing else */
+ case 0x38: /* alt pressed */
+ alt = 1;
+ return; /* do nothing else */
+ case 0xB8: /* alt released */
+ alt = 0;
+ return; /* do nothing else */
+ case 0x1d: /* ctrl pressed */
+ ctrl = 1;
+ return; /* do nothing else */
+ case 0x9d: /* ctrl released */
+ ctrl = 0;
+ return; /* do nothing else */
+ case 0x46: /* scrollock pressed */
+ scroll_lock = ~scroll_lock;
+ kbd_set_leds ();
+ return; /* do nothing else */
+ case 0x3A: /* capslock pressed */
+ caps_lock = ~caps_lock;
+ kbd_set_leds ();
+ return;
+ case 0x45: /* numlock pressed */
+ num_lock = ~num_lock;
+ kbd_set_leds ();
+ return;
+ case 0xC6: /* scroll lock released */
+ case 0xC5: /* num lock released */
+ case 0xBA: /* caps lock released */
+ return; /* just swallow */
}
- if((scancode&0x80)==0x80) /* key released */
+ if ((scancode & 0x80) == 0x80) /* key released */
return;
/* now, decide which table we need */
- if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown scancode %X\n",scancode);
- return; /* swallow it */
+ if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown scancode %X\n", scancode);
+ return; /* swallow it */
}
/* setup plain code first */
- keycode=kbd_plain_xlate[scancode];
- if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
- if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown caps-locked scancode %X\n",scancode);
- return; /* swallow it */
+ keycode = kbd_plain_xlate[scancode];
+ if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */
+ if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown caps-locked scancode %X\n", scancode);
+ return; /* swallow it */
}
- keycode=kbd_shift_xlate[scancode];
- if(keycode<'A') { /* we only want the alphas capital */
- keycode=kbd_plain_xlate[scancode];
+ keycode = kbd_shift_xlate[scancode];
+ if (keycode < 'A') { /* we only want the alphas capital */
+ keycode = kbd_plain_xlate[scancode];
}
}
- if(shift==1) { /* shift overwrites caps_lock */
- if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown shifted scancode %X\n",scancode);
- return; /* swallow it */
+ if (shift == 1) { /* shift overwrites caps_lock */
+ if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown shifted scancode %X\n", scancode);
+ return; /* swallow it */
}
- keycode=kbd_shift_xlate[scancode];
+ keycode = kbd_shift_xlate[scancode];
}
- if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
- if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown ctrl scancode %X\n",scancode);
- return; /* swallow it */
+ if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */
+ if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown ctrl scancode %X\n", scancode);
+ return; /* swallow it */
}
- keycode=kbd_ctrl_xlate[scancode];
+ keycode = kbd_ctrl_xlate[scancode];
}
/* check if valid keycode */
- if(keycode==0xff) {
- PRINTF("unkown scancode %X\n",scancode);
- return; /* swallow unknown codes */
+ if (keycode == 0xff) {
+ PRINTF ("unkown scancode %X\n", scancode);
+ return; /* swallow unknown codes */
}
- kbd_put_queue(keycode);
- PRINTF("%x\n",keycode);
+ kbd_put_queue (keycode);
+ PRINTF ("%x\n", keycode);
}
/*
@@ -583,8 +582,7 @@ char * kbd_initialize(void)
status = kbd_wait_for_input();
if (status == KBD_REPLY_ACK)
break;
- if (status != KBD_REPLY_RESEND)
- {
+ if (status != KBD_REPLY_RESEND) {
PRINTF("status: %X\n",status);
return "Kbd: reset failed, no ACK";
}
diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
index 1d28513..1393ea1 100644
--- a/board/mpl/common/memtst.c
+++ b/board/mpl/common/memtst.c
@@ -55,9 +55,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define FALSE 0
#define TRUE 1
-#define TEST_QUIET 8
-#define TEST_SHOW_PROG 4
-#define TEST_SHOW_ERR 2
+#define TEST_QUIET 8
+#define TEST_SHOW_PROG 4
+#define TEST_SHOW_ERR 2
#define TEST_SHOW_ALL 1
#define TESTPAT1 0xAA55AA55
@@ -473,19 +473,19 @@ void mem_test_reloc(void)
unsigned long addr;
int i;
for (i=0; i< TEST_STAGES; i++) {
- addr = (ulong) (test_stage[i].test_write) + gd->reloc_off;
+ addr = (ulong) (test_stage[i].test_write) + gd->reloc_off;
test_stage[i].test_write=
(void (*) (unsigned long startaddr, unsigned long size,
unsigned long *pat))addr;
- addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off;
+ addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off;
test_stage[i].test_write_desc=(char *)addr;
- if(test_stage[i].test_check1) {
+ if(test_stage[i].test_check1) {
addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off;
test_stage[i].test_check1=
(void *(*) (int mode, unsigned long startaddr,
unsigned long size, unsigned long *pat))addr;
}
- if(test_stage[i].test_check2) {
+ if(test_stage[i].test_check2) {
addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off;
test_stage[i].test_check2=
(void *(*) (int mode, unsigned long startaddr,
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
index bde14be..bfd6428 100644
--- a/board/mpl/common/pci.c
+++ b/board/mpl/common/pci.c
@@ -97,7 +97,7 @@ static void reloc_pci_cfg_table(struct pci_config_table *table)
unsigned long addr;
for (; table && table->vendor; table++) {
- addr = (ulong) (table->config_device) + gd->reloc_off;
+ addr = (ulong) (table->config_device) + gd->reloc_off;
#ifdef DEBUG
printf ("device \"%d\": 0x%08lx => 0x%08lx\n",
table->device, (ulong) (table->config_device), addr);
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
index 60008e2..7bca961 100644
--- a/board/mpl/common/pci_parts.h
+++ b/board/mpl/common/pci_parts.h
@@ -80,9 +80,9 @@
*/
struct pci_pip405_config_entry {
- int index; /* address */
- unsigned long val; /* value */
- int width; /* data size */
+ int index; /* address */
+ unsigned long val; /* value */
+ int width; /* data size */
};
extern void pci_pip405_write_regs(struct pci_controller *,
@@ -95,37 +95,37 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
{PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
{PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
{PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
- {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
+ {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
#if defined(CONFIG_PIP405)
- {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */
- {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */
+ {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */
+ {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */
#endif
{PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */
- { } /* end of device table */
+ { } /* end of device table */
};
/* PIIX4 IDE Controller Function 1 */
static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
{PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
- {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
+ {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
#if !defined(CONFIG_MIP405T)
{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
#else
{PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
#endif
- { } /* end of device table */
+ { } /* end of device table */
};
/* PIIX4 USB Controller Function 2 */
static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
#if !defined(CONFIG_MIP405T)
- {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
+ {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
{PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
- {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
- {0xC0, 0x2000, 2}, /* Legacy support */
+ {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
+ {0xC0, 0x2000, 2}, /* Legacy support */
{PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */
#endif
- { } /* end of device table */
+ { } /* end of device table */
};
/* PIIX4 Power Management Function 3 */
@@ -133,12 +133,12 @@ static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
{PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
{PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
{PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
- {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
- { } /* end of device table */
+ {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
+ { } /* end of device table */
};
/* PPC405 Dummy only used to prevent autosetup on this host bridge */
static struct pci_pip405_config_entry ppc405_dummy[] = {
- { } /* end of device table */
+ { } /* end of device table */
};
void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
@@ -146,13 +146,13 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
static struct pci_config_table pci_pip405_config_table[]={
- {PCI_VENDOR_ID_IBM, /* 405 dummy */
+ {PCI_VENDOR_ID_IBM, /* 405 dummy */
PCI_DEVICE_ID_IBM_405GP,
PCI_ANY_ID,
PCI_ANY_ID, PCI_ANY_ID, 0,
pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
- {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
+ {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
PCI_DEVICE_ID_INTEL_82371AB_0,
PCI_ANY_ID,
PCI_ANY_ID, PCI_ANY_ID, 0,
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
index 84c91c4..6778e40 100644
--- a/board/mpl/common/usb_uhci.c
+++ b/board/mpl/common/usb_uhci.c
@@ -540,7 +540,7 @@ void usb_check_int_chain(void)
link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
td=(uhci_td_t *)link; /* assign it */
/* all interrupt TDs are finally linked to the td_int[0].
- * so we process all until we find the td_int[0].
+ * so we process all until we find the td_int[0].
* if int0 chain points to a QH, we're also done
*/
while(((i>0) && (link != (unsigned long)&td_int[0])) ||
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
index 6fbc585..6ad95b5 100644
--- a/board/mpl/mip405/cmd_mip405.c
+++ b/board/mpl/mip405/cmd_mip405.c
@@ -38,19 +38,19 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- ulong led_on;
+ ulong led_on;
if (strcmp(argv[1], "info") == 0)
{
print_mip405_info();
- return 0;
- }
- if (strcmp(argv[1], "led") == 0)
+ return 0;
+ }
+ if (strcmp(argv[1], "led") == 0)
{
led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
user_led0(led_on);
return 0;
- }
+ }
return (do_mplcommon(cmdtp, flag, argc, argv));
}
U_BOOT_CMD(
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 4b1c1c0..9e8f9bb 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -89,12 +89,12 @@ extern ldiv_t ldiv (long int __numer, long int __denom);
#endif
-#define PLD_PART_REG PER_PLD_ADDR + 0
-#define PLD_VERS_REG PER_PLD_ADDR + 1
-#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
-#define PLD_IRQ_REG PER_PLD_ADDR + 3
-#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
-#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
+#define PLD_PART_REG PER_PLD_ADDR + 0
+#define PLD_VERS_REG PER_PLD_ADDR + 1
+#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
+#define PLD_IRQ_REG PER_PLD_ADDR + 3
+#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
+#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
#define MEGA_BYTE (1024*1024)
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
index b1d91de..fd7e78a 100644
--- a/board/mpl/mip405/mip405.h
+++ b/board/mpl/mip405/mip405.h
@@ -35,7 +35,7 @@ void user_led0(unsigned char on);
#endif
/* timings */
/* PLD (CS7) */
-#define PLD_BME 0 /* Burst disable */
+#define PLD_BME 0 /* Burst disable */
#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define PLD_OEN 1 /* Cycles from CS low to OE low */
@@ -46,7 +46,7 @@ void user_led0(unsigned char on);
#define PLD_SOR 1 /* Sample on Ready disabled */
#define PLD_BEM 0 /* Byte Write only active on Write cycles */
#define PLD_PEN 0 /* Parity disable */
-#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
+#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -62,7 +62,7 @@ void user_led0(unsigned char on);
#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
/* Dummy CS to get the board revision */
-#define BOARD_BME 0 /* Burst disable */
+#define BOARD_BME 0 /* Burst disable */
#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define BOARD_OEN 1 /* Cycles from CS low to OE low */
@@ -73,7 +73,7 @@ void user_led0(unsigned char on);
#define BOARD_SOR 1 /* Sample on Ready disabled */
#define BOARD_BEM 0 /* Byte Write only active on Write cycles */
#define BOARD_PEN 0 /* Parity disable */
-#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
+#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -86,7 +86,7 @@ void user_led0(unsigned char on);
/* UART0 CS2 */
-#define UART0_BME 0 /* Burst disable */
+#define UART0_BME 0 /* Burst disable */
#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define UART0_OEN 1 /* Cycles from CS low to OE low */
@@ -97,7 +97,7 @@ void user_led0(unsigned char on);
#define UART0_SOR 1 /* Sample on Ready disabled */
#define UART0_BEM 0 /* Byte Write only active on Write cycles */
#define UART0_PEN 0 /* Parity disable */
-#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
+#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -115,10 +115,10 @@ void user_led0(unsigned char on);
/* Flash CS0 or CS 1 */
/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B 1 /* Burst enable */
+#define FLASH_BME_B 1 /* Burst enable */
#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME 0 /* Burst disable */
+#define FLASH_BME 0 /* Burst disable */
#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define FLASH_OEN 1 /* Cycles from CS low to OE low */
@@ -130,10 +130,10 @@ void user_led0(unsigned char on);
#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
#define FLASH_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
-#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Access Parameter Register for Boot */
-#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -149,10 +149,10 @@ void user_led0(unsigned char on);
/* MPS CS1 or CS0 */
/* Boot CS: */
-#define MPS_BME_B 1 /* Burst enable */
+#define MPS_BME_B 1 /* Burst enable */
#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME 0 /* Burst disable */
+#define MPS_BME 0 /* Burst disable */
#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define MPS_OEN 1 /* Cycles from CS low to OE low */
@@ -164,10 +164,10 @@ void user_led0(unsigned char on);
#define MPS_BEM 0 /* Byte Write only active on Write cycles */
#define MPS_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
-#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Access Parameter Register for Boot */
-#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds
index ffdf467..7932b9f 100644
--- a/board/mpl/mip405/u-boot.lds
+++ b/board/mpl/mip405/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
+ .rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
index 98429c0..91683a3 100644
--- a/board/mpl/pati/cmd_pati.c
+++ b/board/mpl/pati/cmd_pati.c
@@ -360,12 +360,12 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (strcmp(argv[1], "info") == 0)
{
show_pld_regs();
- return 0;
+ return 0;
}
if (strcmp(argv[1], "pci") == 0)
{
display_pci_regs();
- return 0;
+ return 0;
}
if (strcmp(argv[1], "led") == 0)
{
@@ -377,7 +377,7 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
user_led1(led_on);
return 0;
- }
+ }
#if defined(CFG_PCI_CON_DEVICE)
if (strcmp(argv[1], "con") == 0) {
pci_con_connect();
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
index 0355b65..7893d61 100644
--- a/board/mpl/pati/pati.c
+++ b/board/mpl/pati/pati.c
@@ -484,7 +484,7 @@ int pci_con_getc(void)
else
diff=r_ptr-w_ptr;
if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
- /* clear Mail box */
+ /* clear Mail box */
buff_full=0;
PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
}
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
index d521772..86c7a41 100644
--- a/board/mpl/pati/pati.h
+++ b/board/mpl/pati/pati.h
@@ -89,7 +89,7 @@
#define SDRAM_CAL 9
#define SDRAM_RCD 10
#define SDRAM_WREQ 11
-#define SDRAM_PR 12
+#define SDRAM_PR 12
#define SDRAM_RC 13
#define SDRAM_LMR 14
#define SDRAM_IIP 19
@@ -128,7 +128,7 @@
#define SDRAM_MUX0 9
#define SDRAM_MUX1 10
#define SDRAM_PDIS 11
-#define SDRAM_RES1 12
+#define SDRAM_RES1 12
#define SDRAM_RES2 13
#define SDRAM_RES3 14
#define SDRAM_RES4 19
@@ -177,7 +177,7 @@
#define SDRAM_RES5 9
#define SDRAM_CFG1 10
#define SDRAM_CFG2 11
-#define SDRAM_CFG3 12
+#define SDRAM_CFG3 12
#define SDRAM_RES6 13
#define SDRAM_CFG5 14
#define SDRAM_CFG6 19
@@ -214,7 +214,7 @@
* MISC Defines
***************************************************************/
-#define PCI_VENDOR_ID_MPL 0x18E6
+#define PCI_VENDOR_ID_MPL 0x18E6
#define PCI_DEVICE_ID_PATI 0x00DA
#if defined(CONFIG_MIP405)
@@ -269,12 +269,12 @@
/* Config Area */
#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */
-#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */
+#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */
/* Attributes */
-#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
-#define PATI_LOC_CFG_BURST 0 /* No Burst */
-#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */
-#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */
+#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_CFG_BURST 0 /* No Burst */
+#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */
#define PATI_LOC_CFG_SPACE0_ATTR ( \
PATI_LOC_CFG_BUS_SIZE | \
@@ -295,10 +295,10 @@
#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */
#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */
/* Attributes */
-#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
-#define PATI_LOC_SDRAM_BURST 0 /* No Burst */
-#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */
-#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */
+#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_SDRAM_BURST 0 /* No Burst */
+#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */
+#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */
/* should never be used */
#define PATI_LOC_SDRAM_SPACE0_ATTR ( \
@@ -319,10 +319,10 @@
#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */
#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */
/* Attributes */
-#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */
-#define PATI_LOC_FLASH_BURST 0 /* No Burst */
-#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */
-#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */
+#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */
+#define PATI_LOC_FLASH_BURST 0 /* No Burst */
+#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */
/* should never be used */
#define PATI_LOC_FLASH_SPACE0_ATTR ( \
@@ -343,7 +343,7 @@
#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */
#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */
/* Attributes */
-#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
#define PATI_LOC_CPU_BURST 0 /* No Burst */
#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */
#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */
@@ -393,9 +393,9 @@
#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
-#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
-#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
+#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
/***************************************************
* Direct Master Config
@@ -404,12 +404,12 @@
#define PATI_BUS_MASTER 1
-#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */
-#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */
+#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */
+#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */
-#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */
-#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */
-#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */
+#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */
+#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */
+#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */
#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000
#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008
#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
index 9658808..af34b86 100644
--- a/board/mpl/pati/pci_eeprom.h
+++ b/board/mpl/pati/pci_eeprom.h
@@ -35,57 +35,57 @@ typedef struct pci_eeprom_t {
} pci_eeprom;
static pci_eeprom pati_eeprom[] = {
- { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */
- { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */
- { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */
- { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
- { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
- { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
- { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
- { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
- { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
- { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
- { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
- { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
- { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
- { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
- { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
- { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
- { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
- { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
- { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
- { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */
- { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
- { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
- { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
- { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
- { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
- { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
- { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
- { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
- { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
- { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
- { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
- { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
- { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
- { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
- { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */
- { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */
- { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
- { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
- { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
- { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
- { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
- { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
- { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */
- { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
- { 0x58,0x0000 }, /* Reserved Reserved */
- { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
- { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */
- { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
- { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
- { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */
- { 0xFFFF,0xFFFF} /* terminaror */
+ { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */
+ { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */
+ { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */
+ { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
+ { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
+ { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
+ { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
+ { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
+ { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
+ { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
+ { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
+ { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
+ { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
+ { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
+ { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
+ { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
+ { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
+ { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
+ { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
+ { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */
+ { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
+ { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
+ { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
+ { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
+ { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
+ { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
+ { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
+ { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
+ { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
+ { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
+ { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
+ { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
+ { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
+ { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
+ { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */
+ { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */
+ { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
+ { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
+ { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
+ { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
+ { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
+ { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
+ { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */
+ { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
+ { 0x58,0x0000 }, /* Reserved Reserved */
+ { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
+ { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */
+ { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
+ { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
+ { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */
+ { 0xFFFF,0xFFFF} /* terminaror */
};
#define PATI_EEPROM_LAST_OFFSET 0x64
#endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c
index 1bf4d7b..945e5c9 100644
--- a/board/mpl/pip405/cmd_pip405.c
+++ b/board/mpl/pip405/cmd_pip405.c
@@ -38,14 +38,14 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- ulong led_on,led_nr;
+ ulong led_on,led_nr;
if (strcmp(argv[1], "info") == 0)
{
print_pip405_info();
- return 0;
- }
- if (strcmp(argv[1], "led") == 0)
+ return 0;
+ }
+ if (strcmp(argv[1], "led") == 0)
{
led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
@@ -54,7 +54,7 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
user_led1(led_on);
return 0;
- }
+ }
return (do_mplcommon(cmdtp, flag, argc, argv));
}
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
index b41c5bb..5815786 100644
--- a/board/mpl/pip405/pip405.h
+++ b/board/mpl/pip405/pip405.h
@@ -56,7 +56,7 @@ void user_led1(unsigned char on);
/* timings */
/* CS Config register (CS7) */
-#define CONFIG_PORT_BME 0 /* Burst disable */
+#define CONFIG_PORT_BME 0 /* Burst disable */
#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */
@@ -67,7 +67,7 @@ void user_led1(unsigned char on);
#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */
#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */
#define CONFIG_PORT_PEN 0 /* Parity disable */
-#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -80,10 +80,10 @@ void user_led1(unsigned char on);
/* Flash CS0 or CS 1 */
/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B 1 /* Burst enable */
+#define FLASH_BME_B 1 /* Burst enable */
#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME 0 /* Burst disable */
+#define FLASH_BME 0 /* Burst disable */
#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define FLASH_OEN 1 /* Cycles from CS low to OE low */
@@ -95,10 +95,10 @@ void user_led1(unsigned char on);
#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
#define FLASH_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
-#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Access Parameter Register for Boot */
-#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -114,10 +114,10 @@ void user_led1(unsigned char on);
/* MPS CS1 or CS0 */
/* Boot CS: */
-#define MPS_BME_B 1 /* Burst enable */
+#define MPS_BME_B 1 /* Burst enable */
#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME 0 /* Burst disable */
+#define MPS_BME 0 /* Burst disable */
#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define MPS_OEN 1 /* Cycles from CS low to OE low */
@@ -129,10 +129,10 @@ void user_led1(unsigned char on);
#define MPS_BEM 0 /* Byte Write only active on Write cycles */
#define MPS_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
-#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Access Parameter Register for Boot */
-#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds
index c7ae4d0..fb71064 100644
--- a/board/mpl/pip405/u-boot.lds
+++ b/board/mpl/pip405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
+ .rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
index 88dcaf9..0552994 100644
--- a/board/mpl/pip405/u-boot.lds.debug
+++ b/board/mpl/pip405/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
+ .rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
index 90a1b08..d3629c5 100644
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -58,8 +58,8 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (strcmp(argv[1], "info") == 0)
{
print_vcma9_info();
- return 0;
- }
+ return 0;
+ }
#if defined(CONFIG_DRIVER_CS8900)
if (strcmp(argv[1], "cs8900") == 0) {
if (strcmp(argv[2], "read") == 0) {
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
index a023353..e3af073 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -39,92 +39,92 @@
#define SDRAM_REG 0x2C000106
/* BWSCON */
-#define DW8 (0x0)
-#define DW16 (0x1)
-#define DW32 (0x2)
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
/* BANKSIZE */
#define BURST_EN (0x1<<7)
-#define B1_BWSCON (DW16)
-#define B2_BWSCON (DW32)
-#define B3_BWSCON (DW32)
-#define B4_BWSCON (DW16 + WAIT + UBLB)
-#define B5_BWSCON (DW8 + UBLB)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
+#define B1_BWSCON (DW16)
+#define B2_BWSCON (DW32)
+#define B3_BWSCON (DW32)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW8 + UBLB)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
/* BANK0CON */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x1 /* 1clk */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x1 /* 1clk */
/*#define B0_Tcos 0x0 0clk */
-#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tacc 0x7 /* 14clk */
/*#define B0_Tacc 0x5 8clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0 /* page mode is not used */
-#define B0_PMC 0x0 /* page mode disabled */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* page mode is not used */
+#define B0_PMC 0x0 /* page mode disabled */
/* BANK1CON */
-#define B1_Tacs 0x0 /* 0clk */
-#define B1_Tcos 0x1 /* 1clk */
+#define B1_Tacs 0x0 /* 0clk */
+#define B1_Tcos 0x1 /* 1clk */
/*#define B1_Tcos 0x0 0clk */
#define B1_Tacc 0x7 /* 14clk */
/*#define B1_Tacc 0x5 8clk */
-#define B1_Tcoh 0x0 /* 0clk */
-#define B1_Tah 0x0 /* 0clk */
-#define B1_Tacp 0x0 /* page mode is not used */
-#define B1_PMC 0x0 /* page mode disabled */
-
-#define B2_Tacs 0x3 /* 4clk */
-#define B2_Tcos 0x3 /* 4clk */
-#define B2_Tacc 0x7 /* 14clk */
-#define B2_Tcoh 0x3 /* 4clk */
-#define B2_Tah 0x3 /* 4clk */
-#define B2_Tacp 0x0 /* page mode is not used */
-#define B2_PMC 0x0 /* page mode disabled */
-
-#define B3_Tacs 0x3 /* 4clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x3 /* 4clk */
-#define B3_Tah 0x3 /* 4clk */
-#define B3_Tacp 0x0 /* page mode is not used */
-#define B3_PMC 0x0 /* page mode disabled */
-
-#define B4_Tacs 0x3 /* 4clk */
-#define B4_Tcos 0x1 /* 1clk */
-#define B4_Tacc 0x7 /* 14clk */
-#define B4_Tcoh 0x1 /* 1clk */
-#define B4_Tah 0x0 /* 0clk */
-#define B4_Tacp 0x0 /* page mode is not used */
-#define B4_PMC 0x0 /* page mode disabled */
-
-#define B5_Tacs 0x0 /* 0clk */
-#define B5_Tcos 0x3 /* 4clk */
-#define B5_Tacc 0x5 /* 8clk */
-#define B5_Tcoh 0x2 /* 2clk */
-#define B5_Tah 0x1 /* 1clk */
-#define B5_Tacp 0x0 /* page mode is not used */
-#define B5_PMC 0x0 /* page mode disabled */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1 /* 3clk */
-#define B6_SCAN 0x2 /* 10bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 3clk */
-#define B7_SCAN 0x2 /* 10bit */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0 /* page mode is not used */
+#define B1_PMC 0x0 /* page mode disabled */
+
+#define B2_Tacs 0x3 /* 4clk */
+#define B2_Tcos 0x3 /* 4clk */
+#define B2_Tacc 0x7 /* 14clk */
+#define B2_Tcoh 0x3 /* 4clk */
+#define B2_Tah 0x3 /* 4clk */
+#define B2_Tacp 0x0 /* page mode is not used */
+#define B2_PMC 0x0 /* page mode disabled */
+
+#define B3_Tacs 0x3 /* 4clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x3 /* 4clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0 /* page mode is not used */
+#define B3_PMC 0x0 /* page mode disabled */
+
+#define B4_Tacs 0x3 /* 4clk */
+#define B4_Tcos 0x1 /* 1clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x1 /* 1clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0 /* page mode is not used */
+#define B4_PMC 0x0 /* page mode disabled */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x3 /* 4clk */
+#define B5_Tacc 0x5 /* 8clk */
+#define B5_Tcoh 0x2 /* 2clk */
+#define B5_Tah 0x1 /* 1clk */
+#define B5_Tacp 0x0 /* page mode is not used */
+#define B5_PMC 0x0 /* page mode disabled */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1 /* 3clk */
+#define B6_SCAN 0x2 /* 10bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x2 /* 10bit */
/* REFRESH parameter */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp 0x0 /* 2clk */
-#define Trc 0x3 /* 7clk */
-#define Tchr 0x2 /* 3clk */
-#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
_TEXT_BASE:
generated by cgit v1.1 at 2024-11-10 08:00:53 +0000