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-rw-r--r--board/mpl/pip405/pip405.c8
-rw-r--r--board/mpl/pip405/pip405.h2
-rw-r--r--board/mpl/pip405/u-boot.lds3
-rw-r--r--board/mpl/pip405/u-boot.lds.debug2
4 files changed, 8 insertions, 7 deletions
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index 6cba892..8724e27 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -208,7 +208,7 @@ int board_early_init_f (void)
#endif
/* Read Serial Presence Detect Information */
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
dataout[0] = 0;
for (i = 0; i < 128; i++)
datain[i] = 127;
@@ -252,7 +252,7 @@ int board_early_init_f (void)
(datain[2] != 0x04) || /* if not SDRAM */
(!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
(datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
- (datain[126] == 0x66)) /* or a 66Mhz modules */
+ (datain[126] == 0x66)) /* or a 66MHz modules */
SDRAM_err ("unsupported SDRAM");
#ifdef SDRAM_DEBUG
serial_puts ("SDRAM sanity ok\n");
@@ -386,7 +386,7 @@ int board_early_init_f (void)
/* write SDRAM timing register */
mtdcr (memcfga, mem_sdtr1);
mtdcr (memcfgd, tmp);
- baseaddr = CFG_SDRAM_BASE;
+ baseaddr = CONFIG_SYS_SDRAM_BASE;
bank_size = (((unsigned long) density) << 22) / 2;
/* insert AM value */
tmp = ((unsigned long) t->mode - 1) << 13;
@@ -663,7 +663,7 @@ int misc_init_r (void)
{
/* adjust flash start and size as well as the offset */
gd->bd->bi_flashstart=0-flash_info[0].size;
- gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+ gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
gd->bd->bi_flashoffset=0;
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
index 5815786..704ab2c 100644
--- a/board/mpl/pip405/pip405.h
+++ b/board/mpl/pip405/pip405.h
@@ -35,7 +35,7 @@ void user_led0(unsigned char on);
void user_led1(unsigned char on);
-#define PLD_BASE_ADDRESS CFG_ISA_IO_BASE_ADDRESS + 0x800
+#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
#define PLD_PART_REG PLD_BASE_ADDRESS + 0
#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2
diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds
index fb71064..afe203b 100644
--- a/board/mpl/pip405/u-boot.lds
+++ b/board/mpl/pip405/u-boot.lds
@@ -74,7 +74,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -145,6 +145,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
index 0552994..338392a 100644
--- a/board/mpl/pip405/u-boot.lds.debug
+++ b/board/mpl/pip405/u-boot.lds.debug
@@ -61,7 +61,7 @@ SECTIONS
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
- common/environment.o(.text)
+ common/env_embedded.o(.text)
*(.text)
*(.fixup)