diff options
Diffstat (limited to 'board/mpl/mip405')
| -rw-r--r-- | board/mpl/mip405/Makefile | 2 | ||||
| -rw-r--r-- | board/mpl/mip405/cmd_mip405.c | 6 | ||||
| -rw-r--r-- | board/mpl/mip405/init.S | 13 | ||||
| -rw-r--r-- | board/mpl/mip405/mip405.c | 3 | ||||
| -rw-r--r-- | board/mpl/mip405/mip405.h | 5 | ||||
| -rw-r--r-- | board/mpl/mip405/u-boot.lds | 5 |
6 files changed, 18 insertions, 16 deletions
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 839cafe..9276f64 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -31,7 +31,7 @@ OBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ SOBJS = init.o $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c index 6ec128f..2075fbd 100644 --- a/board/mpl/mip405/cmd_mip405.c +++ b/board/mpl/mip405/cmd_mip405.c @@ -53,5 +53,11 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return (do_mplcommon(cmdtp, flag, argc, argv)); } +cmd_tbl_t U_BOOT_CMD(mip405) = MK_CMD_ENTRY( + "mip405", 6, 1, do_mip405, + "mip405 - MIP405 specific Cmds\n", + "flash mem [SrcAddr] - updates U-Boot with image in memory\n" + "mip405 flash mps - updates U-Boot with image from MPS\n" +); /* ------------------------------------------------------------------------- */ diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index ad3f78d..00bf739 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -63,7 +63,7 @@ ext_bus_cntlr_init: mtlr r4 /* restore link register */ addi r4,0,14 /* set ctr to 14; used to prefetch */ mtctr r4 /* 14 cache lines to fit this function */ - /* in cache (gives us 8x14=112 instrctns) */ + /* in cache (gives us 8x14=112 instrctns) */ ..ebcloop: icbt r0,r3 /* prefetch cache line for addr in r3 */ addi r3,r3,32 /* move to next cache line */ @@ -116,10 +116,10 @@ ext_bus_cntlr_init: 0: - /* 8Bit boot mode: */ + /* 8Bit boot mode: */ /*----------------------------------------------------------------------- - * Memory Bank 0 Multi Purpose Socket initialization - *----------------------------------------------------------------------- */ + * Memory Bank 0 Multi Purpose Socket initialization + *----------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ addi r4,0,pb0ap mtdcr ebccfga,r4 @@ -133,7 +133,7 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 addi r4,0,pb0cr - mtdcr ebccfga,r4 + mtdcr ebccfga,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ /* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */ /* ori r4,r4,0x8000 / * BW=0x0( 8 bits) */ @@ -197,7 +197,7 @@ ext_bus_cntlr_init: * Description: Configures the internal SRAM memory. and setup the * Stackpointer in it. *----------------------------------------------------------------------------- */ - .globl sdram_init + .globl sdram_init sdram_init: @@ -245,4 +245,3 @@ _start_pci: nop b _start /* normal start */ #endif - diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 93d8679..07922bc 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -511,7 +511,6 @@ unsigned short get_pld_parvers (void) } - void user_led0 (unsigned char on) { if (on) @@ -762,5 +761,3 @@ void print_mip405_info (void) printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); } - - diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h index 101b173..f1e37ff 100644 --- a/board/mpl/mip405/mip405.h +++ b/board/mpl/mip405/mip405.h @@ -32,7 +32,6 @@ extern int mem_test(unsigned long start, unsigned long ramsize,int mode); void user_led0(unsigned char on); - #endif /* timings */ /* PLD (CS7) */ @@ -114,7 +113,6 @@ void user_led0(unsigned char on); #define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) - /* Flash CS0 or CS 1 */ /* 0x7F8FFE80 slowest timing at all... */ #define FLASH_BME_B 1 /* Burst enable */ @@ -182,6 +180,3 @@ void user_led0(unsigned char on); #define MPS_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) /* CR register for non Boot */ #define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) - - - diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds index 710a139..bb0f122 100644 --- a/board/mpl/mip405/u-boot.lds +++ b/board/mpl/mip405/u-boot.lds @@ -125,6 +125,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; __ex_table : { *(__ex_table) } __stop___ex_table = .; |