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-rw-r--r--board/mpl/mip405/cmd_mip405.c5
-rw-r--r--board/mpl/mip405/init.S24
-rw-r--r--board/mpl/mip405/mip405.c7
-rw-r--r--board/mpl/mip405/mip405.h7
4 files changed, 20 insertions, 23 deletions
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
index 0f28fa2..6fbc585 100644
--- a/board/mpl/mip405/cmd_mip405.c
+++ b/board/mpl/mip405/cmd_mip405.c
@@ -54,10 +54,13 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (do_mplcommon(cmdtp, flag, argc, argv));
}
U_BOOT_CMD(
- mip405, 6, 1, do_mip405,
+ mip405, 8, 1, do_mip405,
"mip405 - MIP405 specific Cmds\n",
"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
"mip405 flash mps - updates U-Boot with image from MPS\n"
+ "mip405 info - displays board information\n"
+ "mip405 led <on> - switches LED on (on=1) or off (on=0)\n"
+ "mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever\n"
);
/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
index 00bf739..3351b5b 100644
--- a/board/mpl/mip405/init.S
+++ b/board/mpl/mip405/init.S
@@ -87,19 +87,15 @@ ext_bus_cntlr_init:
mfdcr r4,ebccfgd
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
- beq 0f /* jump if 8 bit bus width */
+ beq 0f /* jump if 8 bit bus width */
- /* setup 16 bit things (Flash Boot)
+ /* setup 16 bit things
*-----------------------------------------------------------------------
* Memory Bank 0 (16 Bit Flash) initialization
*---------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
-/* addis r4,0,0xFF8F */
-/* ori r4,r4,0xFE80 */
-/* addis r4,0,0x9B01 */
-/* ori r4,r4,0x5480 */
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
mtdcr ebccfgd,r4
@@ -107,8 +103,6 @@ ext_bus_cntlr_init:
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
-/* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/* ori r4,r4,0xA000 / * BW=0x01(16 bits) */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
mtdcr ebccfgd,r4
@@ -123,21 +117,13 @@ ext_bus_cntlr_init:
/* 0x7F8FFE80 slowest boot */
addi r4,0,pb0ap
mtdcr ebccfga,r4
-#if 0
- addis r4,0,0x9B01
- ori r4,r4,0x5480
-#else
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
-#endif
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
-/* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/* ori r4,r4,0x8000 / * BW=0x0( 8 bits) */
-
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
@@ -178,18 +164,18 @@ ext_bus_cntlr_init:
ori r4,r4,0x0000
mtdcr ebccfgd,r4
- addi r4,0,pb6cr
+ addi r4,0,pb6cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
- addi r4,0,pb7cr
+ addi r4,0,pb7cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
- nop /* pass2 DCR errata #8 */
+ nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 090041b..70eb5f4 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -667,9 +667,16 @@ static int test_dram (unsigned long ramsize)
/* used to check if the time in RTC is valid */
static unsigned long start;
static struct rtc_time tm;
+extern flash_info_t flash_info[]; /* info for FLASH chips */
int misc_init_r (void)
{
+ DECLARE_GLOBAL_DATA_PTR;
+ /* adjust flash start and size as well as the offset */
+ gd->bd->bi_flashstart=0-flash_info[0].size;
+ gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+ gd->bd->bi_flashoffset=0;
+
/* check, if RTC is running */
rtc_get (&tm);
start=get_timer(0);
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
index f1e37ff..b1d91de 100644
--- a/board/mpl/mip405/mip405.h
+++ b/board/mpl/mip405/mip405.h
@@ -137,13 +137,13 @@ void user_led0(unsigned char on);
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS 2 /* 4 MByte */
+#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define FLASH_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define FLASH_BW 1 /* 16Bit */
/* CR register for Boot */
-#define FLASH_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
/* CR register for non Boot */
#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
@@ -172,11 +172,12 @@ void user_led0(unsigned char on);
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define MPS_BS 2 /* 4 MByte */
+#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define MPS_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define MPS_BW 0 /* 8Bit */
/* CR register for Boot */
-#define MPS_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
/* CR register for non Boot */
#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
generated by cgit v1.1 at 2024-11-17 06:06:52 +0000