1 files changed, 140 insertions, 74 deletions

diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c
index d02a7ef..c6b2a5b 100644
--- a/board/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/mpc8641hpcn/mpc8641hpcn.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
@@ -25,6 +25,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
@@ -35,20 +36,23 @@
 extern void ft_cpu_setup(void *blob, bd_t *bd);
 #endif
 
+#include "pixis.h"
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
 
-void local_bus_init(void);
 void sdram_init(void);
 long int fixed_sdram(void);
 
 
 int board_early_init_f (void)
 {
-    return 0;
+	return 0;
 }
 
 int checkboard (void)
@@ -57,41 +61,34 @@ int checkboard (void)
 
 #ifdef CONFIG_PCI
 
-        volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-        volatile ccsr_gur_t *gur = &immap->im_gur;
-        volatile ccsr_pex_t *pex1 = &immap->im_pex1;
-
-        uint devdisr = gur->devdisr;
-        uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
-        uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
-        uint pex1_agent =  (host1_agent == 0) || (host1_agent == 1);
-
-        
-        if ((io_sel==2 || io_sel==3 || io_sel==5 \
-	     || io_sel==6 || io_sel==7 || io_sel==0xF)
-	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
-		debug ("PCI-EXPRESS 1: %s \n",
-		       pex1_agent ? "Agent" : "Host");
-                debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
-                if (pex1->pme_msg_det) {
-                        pex1->pme_msg_det = 0xffffffff;
-                        debug (" with errors.  Clearing.  Now 0x%08x",
-			       pex1->pme_msg_det);
-                }
-                debug ("\n");
-        } else {
-                printf ("PCI-EXPRESS 1: Disabled\n");
-        }
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_pex_t *pex1 = &immap->im_pex1;
+
+	uint devdisr = gur->devdisr;
+	uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+	uint pex1_agent =  (host1_agent == 0) || (host1_agent == 1);
+
+	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+		debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
+		if (pex1->pme_msg_det) {
+			pex1->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+			      pex1->pme_msg_det);
+		}
+		debug ("\n");
+	} else {
+		puts("PCI-EXPRESS 1: Disabled\n");
+	}
 
 #else
-	printf("PCI-EXPRESS1: Disabled\n");
+	puts("PCI-EXPRESS1: Disabled\n");
 #endif
 
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init();
-
 	return 0;
 }
 
@@ -100,7 +97,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
 
 #if defined(CONFIG_SPD_EEPROM)
 	dram_size = spd_sdram ();
@@ -112,7 +108,7 @@ initdram(int board_type)
 	puts("    DDR: ");
 	return dram_size;
 #endif
-	
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize and enable DDR ECC.
@@ -125,34 +121,6 @@ initdram(int board_type)
 }
 
 
-/*
- * Initialize Local Bus
- */
-
-void
-local_bus_init(void)
-{
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
-	uint clkdiv;
-	uint lbc_hz;
-	sys_info_t sysinfo;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
-	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-}
-
 #if defined(CFG_DRAM_TEST)
 int testdram(void)
 {
@@ -160,7 +128,7 @@ int testdram(void)
 	uint *pend = (uint *) CFG_MEMTEST_END;
 	uint *p;
 
-	printf("SDRAM test phase 1:\n");
+	puts("SDRAM test phase 1:\n");
 	for (p = pstart; p < pend; p++)
 		*p = 0xaaaaaaaa;
 
@@ -171,7 +139,7 @@ int testdram(void)
 		}
 	}
 
-	printf("SDRAM test phase 2:\n");
+	puts("SDRAM test phase 2:\n");
 	for (p = pstart; p < pend; p++)
 		*p = 0x55555555;
 
@@ -182,7 +150,7 @@ int testdram(void)
 		}
 	}
 
-	printf("SDRAM test passed.\n");
+	puts("SDRAM test passed.\n");
 	return 0;
 }
 #endif
@@ -207,9 +175,9 @@ long int fixed_sdram(void)
 	ddr->sdram_mode_1 = CFG_DDR_MODE_1;
 	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
 	ddr->sdram_interval = CFG_DDR_INTERVAL;
-        ddr->sdram_data_init = CFG_DDR_DATA_INIT;
+	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
 	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
-	ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;	
+	ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
 	ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
 
 #if defined (CONFIG_DDR_ECC)
@@ -217,7 +185,7 @@ long int fixed_sdram(void)
 	ddr->err_sbe = 0x00ff0000;
 #endif
 	asm("sync;isync");
-	
+
 	udelay(500);
 
 #if defined (CONFIG_DDR_ECC)
@@ -228,7 +196,7 @@ long int fixed_sdram(void)
 	ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
 #endif
 	asm("sync; isync");
-	
+
 	udelay(500);
 #endif
 	return CFG_SDRAM_SIZE * 1024 * 1024;
@@ -281,15 +249,113 @@ ft_board_setup(void *blob, bd_t *bd)
 	int len;
 
 	ft_cpu_setup(blob, bd);
-	
+
 	p = ft_get_prop(blob, "/memory/reg", &len);
 	if (p != NULL) {
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
-
 }
 #endif
 
 
+void
+mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char cmd;
+	ulong val;
+	ulong corepll;
 
+	/*
+	 * No args is a simple reset request.
+	 */
+	if (argv <= 0) {
+		out8(PIXIS_BASE + PIXIS_RST, 0);
+		/* not reached */
+	}
+
+	cmd = argv[1][1];
+	switch (cmd) {
+	case 'f':    /* reset with frequency changed */
+		if (argc < 5)
+			goto my_usage;
+		read_from_px_regs(0);
+
+		val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
+
+		corepll = strfractoint(argv[3]);
+		val = val + set_px_corepll(corepll);
+		val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
+		if (val == 3) {
+			puts("Setting registers VCFGEN0 and VCTL\n");
+			read_from_px_regs(1);
+			puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
+			set_px_go();
+		} else
+			goto my_usage;
+
+		while (1); /* Not reached */
+
+	case 'l':
+		if (argv[2][1] == 'f') {
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			/* reset with frequency changed */
+			val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
+
+			corepll = strfractoint(argv[4]);
+			val = val + set_px_corepll(corepll);
+			val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
+			if (val == 3) {
+				puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+				set_altbank();
+				read_from_px_regs(1);
+				read_from_px_regs_altbank(1);
+				puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
+				set_px_go_with_watchdog();
+			} else
+				goto my_usage;
+
+			while(1); /* Not reached */
+
+		} else if(argv[2][1] == 'd'){
+			/*
+			 * Reset from alternate bank without changing
+			 * frequencies but with watchdog timer enabled.
+			 */
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+			set_altbank();
+			read_from_px_regs_altbank(1);
+			puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
+			set_px_go_with_watchdog();
+			while(1); /* Not reached */
+
+		} else {
+			/*
+			 * Reset from next bank without changing
+			 * frequency and without watchdog timer enabled.
+			 */
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			if(argc > 2)
+				goto my_usage;
+			puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
+			set_altbank();
+			read_from_px_regs_altbank(1);
+			puts("Resetting board to boot from the other bank....\n");
+			set_px_go();
+		}
+
+	default:
+		goto my_usage;
+	}
+
+my_usage:
+	puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
+	puts("       reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
+	puts("       reset altbank [wd]\n");
+	puts("For example:   reset cf 40 2.5 10\n");
+	puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
+}