summaryrefslogtreecommitdiff
path: root/board/mpc8540eval
diff options
context:
space:
mode:
Diffstat (limited to 'board/mpc8540eval')
-rw-r--r--board/mpc8540eval/flash.c38
-rw-r--r--board/mpc8540eval/law.c6
-rw-r--r--board/mpc8540eval/mpc8540eval.c70
-rw-r--r--board/mpc8540eval/tlb.c22
4 files changed, 68 insertions, 68 deletions
diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c
index 98fd168..9df5bd9 100644
--- a/board/mpc8540eval/flash.c
+++ b/board/mpc8540eval/flash.c
@@ -31,13 +31,13 @@
#include <common.h>
-#if !defined(CFG_NO_FLASH)
+#if !defined(CONFIG_SYS_NO_FLASH)
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
@@ -74,7 +74,7 @@ unsigned long flash_init (void)
/* Init: enable write,
* or we cannot even write flash commands
*/
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
/* set the default sector offset */
@@ -82,7 +82,7 @@ unsigned long flash_init (void)
/* Static FLASH Bank configuration here - FIXME XXX */
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+ size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -90,16 +90,16 @@ unsigned long flash_init (void)
}
/* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+ size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@@ -177,8 +177,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
udelay(20);
asm("sync");
-#ifndef CFG_FLASH_CFI
- printf("Not define CFG_FLASH_CFI\n");
+#ifndef CONFIG_SYS_FLASH_CFI
+ printf("Not define CONFIG_SYS_FLASH_CFI\n");
return (0);
#else
value = addr[0];
@@ -237,7 +237,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
break;
}
#endif
-#endif /*#ifdef CFG_FLASH_CFI*/
+#endif /*#ifdef CONFIG_SYS_FLASH_CFI*/
if (big_endian==0) value = (addr[0] & 0xFF000000) >>8;
else value = (addr[0] & 0x00FF0000);
@@ -453,7 +453,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
asm("sync");
return 1;
}
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr16 = 0xFFFF; /* reset bank */
asm("sync");
@@ -505,7 +505,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
asm("sync");
return 1;
}
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
@@ -693,7 +693,7 @@ static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt)
/* data polling for D7 */
flag = 0;
while (((csr = *addr) & ready) != ready) {
- if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
@@ -751,7 +751,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
/* data polling for D7 */
flag = 0;
while (((csr = *addr) & ready) != ready) {
- if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
@@ -815,7 +815,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
start = get_timer (0);
flag = 0;
while (((csr = *addr) & ready) != ready) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
@@ -881,7 +881,7 @@ static int clear_block_lock_bit(flash_info_t * info, vu_long * addr)
*addr = 0x70707070; /* read status */
start = get_timer (0);
while((*addr & ready) != ready){
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout on clearing Block Lock Bit\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
@@ -891,4 +891,4 @@ static int clear_block_lock_bit(flash_info_t * info, vu_long * addr)
return 0;
}
-#endif /* !CFG_NO_FLASH */
+#endif /* !CONFIG_SYS_NO_FLASH */
diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c
index cfcd73e..9926d25 100644
--- a/board/mpc8540eval/law.c
+++ b/board/mpc8540eval/law.c
@@ -43,11 +43,11 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
- SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
#ifndef CONFIG_RAM_AS_FLASH
- SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
#endif
};
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 028a70f..9b564b8 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -36,7 +36,7 @@ long int fixed_sdram (void);
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
- volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
+ volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
@@ -53,10 +53,10 @@ int checkboard (void)
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
- if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
- || (CFG_LBC_LCRR & 0x0f) == 8) {
+ if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
+ || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n",
- sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
+ sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
} else {
printf("\tLBC: unknown\n");
}
@@ -69,12 +69,12 @@ phys_size_t initdram (int board_type)
long dram_size = 0;
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
@@ -94,42 +94,42 @@ phys_size_t initdram (int board_type)
dram_size = fixed_sdram ();
#endif
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
return dram_size;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
- if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
- lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+ lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
- lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
- lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
- lbc->br2 = CFG_BR2_PRELIM;
- lbc->lbcr = CFG_LBC_LBCR;
- lbc->lsdmr = CFG_LBC_LSDMR_1;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");
* (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_2;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
asm("sync");
* (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_3;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
asm("sync");
* (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_4;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
asm("sync");
* (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_5;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
asm("sync");
- lbc->lsrt = CFG_LBC_LSRT;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
asm("sync");
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("sync");
#endif
@@ -139,7 +139,7 @@ phys_size_t initdram (int board_type)
* enable errors */
uint *p = 0;
uint i = 0;
- volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -181,11 +181,11 @@ phys_size_t initdram (int board_type)
return dram_size;
}
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
@@ -221,15 +221,15 @@ int testdram (void)
************************************************************************/
long int fixed_sdram (void)
{
-#ifndef CFG_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+#ifndef CONFIG_SYS_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
@@ -238,14 +238,14 @@ long int fixed_sdram (void)
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
- return (CFG_SDRAM_SIZE * 1024 * 1024);
+ return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c
index 1003bf6..06092f8 100644
--- a/board/mpc8540eval/tlb.c
+++ b/board/mpc8540eval/tlb.c
@@ -27,34 +27,34 @@
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
- #if defined(CFG_FLASH_PORT_WIDTH_16)
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ #if defined(CONFIG_SYS_FLASH_PORT_WIDTH_16)
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_4M, 1),
- SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x400000, CFG_FLASH_BASE + 0x400000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x400000, CONFIG_SYS_FLASH_BASE + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_4M, 1),
#else
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_16M, 1),
#endif
#if !defined(CONFIG_SPD_EEPROM)
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
#endif
- SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
#if defined(CONFIG_RAM_AS_FLASH)
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
#else
@@ -62,15 +62,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
#endif
0, 6, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16K, 1),
- SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_16K, 1),
};
generated by cgit v1.1 at 2024-11-17 15:02:11 +0000