diff options
Diffstat (limited to 'board/mpc8540ads')
| -rw-r--r-- | board/mpc8540ads/init.S | 46 | ||||
| -rw-r--r-- | board/mpc8540ads/mpc8540ads.c | 247 |
2 files changed, 164 insertions, 129 deletions
diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S index 486fdc8..99c4d79 100644 --- a/board/mpc8540ads/init.S +++ b/board/mpc8540ads/init.S @@ -45,7 +45,8 @@ tlb1_entry: entry_start - .long 0x0a /* the following data table uses a few of 16 TLB entries */ + /* Number of entries in the following table */ + .long 0x0c .long TLB1_MAS0(1,1,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) @@ -116,40 +117,57 @@ tlb1_entry: .long TLB1_MAS0(1,8,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(1,9,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * RapidIO MMU for 512M + * Two entries, 10 and 11 + */ + .long TLB1_MAS0(1,10,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,11,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) .long TLB1_MAS0(1,15,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #else +#else .long TLB1_MAS0(1,15,0) .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif +#endif entry_end /* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI IO 16M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M * - * Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. */ #if !defined(CONFIG_SPD_EEPROM) @@ -160,7 +178,7 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #endif -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) /* @@ -174,14 +192,14 @@ tlb1_entry: #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #endif -#define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff) +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) /* * Rapid IO at 0xc000_0000 for 512 M */ -#define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) .section .bootpg, "ax" diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 2694d62..a994d16 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -1,4 +1,5 @@ /* + * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2002,2003, Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -24,75 +25,69 @@ */ -extern long int spd_sdram (void); - #include <common.h> #include <asm/processor.h> #include <asm/immap_85xx.h> #include <spd.h> -long int fixed_sdram (void); - #if defined(CONFIG_DDR_ECC) -void dma_init(void); -uint dma_check(void); -int dma_xfer(void *dest, uint count, void *src); +extern void ddr_enable_ecc(unsigned int dram_size); #endif +extern long int spd_sdram(void); + +void sdram_init(void); +long int fixed_sdram(void); -/* MPC8540ADS Board Status & Control Registers */ -#if 0 -typedef struct bscr_ { - unsigned long bcsr0; - unsigned long bcsr1; - unsigned long bcsr2; - unsigned long bcsr3; - unsigned long bcsr4; - unsigned long bcsr5; - unsigned long bcsr6; - unsigned long bcsr7; -} bcsr_t; -#endif int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; - pci->peer &= 0xffffffdf; /* disable master abort */ + pci->peer &= 0xffffffdf; /* disable master abort */ #endif + return 0; } int checkboard (void) { puts("Board: ADS\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + return 0; } -long int initdram (int board_type) +long int +initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); volatile immap_t *immap = (immap_t *)CFG_IMMR; -#if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; -#endif -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; + puts("Initializing\n"); - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } #endif #if defined(CONFIG_SPD_EEPROM) @@ -101,98 +96,120 @@ long int initdram (int board_type) dram_size = fixed_sdram (); #endif -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; +#if defined(CONFIG_DDR_ECC) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init (void) +{ +#if !defined(CONFIG_RAM_AS_FLASH) + sys_info_t sysinfo; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + + puts (" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * LocalBus SDRAM is not emulating flash. + */ + + /* + * Fix Local Bus clock glitch. Errata LBC11. + * + * If localbus freq is less than 66Mhz, use bypass mode, + * otherwise use DLL. + * lcrr is the local-bus clock ratio register. + */ + get_sys_info (&sysinfo); + if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000; + } else { - uint pvr = get_pvr(); + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + volatile ccsr_gur_t *gur = &immap->im_gur; + uint pvr = get_pvr (); + uint temp_lbcdll = 0; if (pvr == PVR_85xx_REV1) { - /* - * Need change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 - * temporarily. - */ - lbc->lcrr = 0x10000004; + lbc->lcrr = 0x10000004; } + + /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; - udelay(200); + udelay (200); temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000; + asm ("sync;isync;msync"); } - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; lbc->br2 = CFG_BR2_PRELIM; lbc->lbcr = CFG_LBC_LBCR; + asm ("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm ("sync"); + + /* + * Configure the SDRAM controller. + */ lbc->lsdmr = CFG_LBC_LSDMR_1; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); + lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); + lbc->lsdmr = CFG_LBC_LSDMR_3; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CFG_LBC_MRTPR; - asm("sync"); -#endif + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - uint *p = 0; - uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - dma_init(); - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } - } + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); - /* 8K */ - dma_xfer((uint *)0x2000,0x2000,(uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000,0x4000,(uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000,0x8000,(uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000,0x10000,(uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000,0x20000,(uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000,0x40000,(uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000,0x80000,(uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000,0x100000,(uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000,0x200000,(uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000,0x400000,(uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); - } + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } #endif - - return dram_size; } @@ -262,6 +279,6 @@ long int fixed_sdram (void) asm("sync; isync; msync"); udelay(500); #endif - return (CFG_SDRAM_SIZE * 1024 * 1024); + return CFG_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ |