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-rw-r--r--board/mpc8360emds/mpc8360emds.c24
-rw-r--r--board/mpc8360emds/pci.c3
2 files changed, 26 insertions, 1 deletions
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
index ddc1047..535884c 100644
--- a/board/mpc8360emds/mpc8360emds.c
+++ b/board/mpc8360emds/mpc8360emds.c
@@ -90,11 +90,18 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
int board_early_init_f(void)
{
- volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
+
+ u8 *bcsr = (u8 *)CFG_BCSR;
+ const immap_t *immr = (immap_t *)CFG_IMMR;
/* Enable flash write */
bcsr[0xa] &= ~0x04;
+ /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
+ if (immr->sysconf.spridr == SPR_8360_REV20 ||
+ immr->sysconf.spridr == SPR_8360E_REV20)
+ bcsr[0xe] = 0x30;
+
return 0;
}
@@ -158,6 +165,20 @@ int fixed_sdram(void)
#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
+#ifdef CONFIG_DDR_II
+ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CFG_DDR_MODE;
+ im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+#else
im->ddr.csbnds[0].csbnds = 0x00000007;
im->ddr.csbnds[1].csbnds = 0x0008000f;
@@ -170,6 +191,7 @@ int fixed_sdram(void)
im->ddr.sdram_mode = CFG_DDR_MODE;
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+#endif
udelay(200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c
index 15a48dc..67cd709 100644
--- a/board/mpc8360emds/pci.c
+++ b/board/mpc8360emds/pci.c
@@ -18,6 +18,9 @@
#include <common.h>
#include <pci.h>
#include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
#include <asm/fsl_i2c.h>