diff options
Diffstat (limited to 'board/mcc200')
| -rw-r--r-- | board/mcc200/mcc200.c | 60 | ||||
| -rw-r--r-- | board/mcc200/mt48lc8m32b2-6-7.h | 18 |
2 files changed, 0 insertions, 78 deletions
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index acc0e06..d1c99fd 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -28,19 +28,12 @@ #include <mpc5xxx.h> #include <pci.h> -//###CHD: es gibt eigentlich kein DDR bei uns -> weg damit!; dto. PCI! -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -//#include "mt48lc16m16a2-75.h" #include "mt48lc8m32b2-6-7.h" -#endif extern flash_info_t flash_info[]; /* FLASH chips info */ ulong flash_get_size (ulong base, int banknum); -//###CHD: wenn RAMBOOT gehen wuerde, .... #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -88,7 +81,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int initdram (int board_type) { ulong dramsize = 0; @@ -190,58 +182,6 @@ long int initdram (int board_type) return dramsize + dramsize2; } -//###CHD: sowas gibt es bei usn nicht! -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { puts ("Board: MCC200\n"); diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h index 6c2b2b3..73dcd5c 100644 --- a/board/mcc200/mt48lc8m32b2-6-7.h +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -4,27 +4,9 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ -//#define SDRAM_MODE 0x00cc0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 -//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104 -//#define SDRAM_CONFIG1 0xe2329000 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 -//#define SDRAM_CONFIG2 0x46e70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C -//Christian -//#define SDRAM_MODE 0x00cd0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 -//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104 -//#define SDRAM_CONFIG1 0xd2322900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 -//#define SDRAM_CONFIG2 0x8ad70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C - -//###CHD: ordentliche Doku dazu! CAS=2, etc. -//STefan #define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 #define SDRAM_CONTROL 0x504f0000 // Control Register—MBAR + 0x0104 #define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 #define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C - - -#else -#error CONFIG_MPC5200 not defined, please set parameters for your sdram controller in mt48lc8m32b2.h -#endif |