diff options
Diffstat (limited to 'board/mcc200')
| -rw-r--r-- | board/mcc200/mcc200.c | 8 | ||||
| -rw-r--r-- | board/mcc200/mt48lc16m32s2-75.h | 43 |
2 files changed, 50 insertions, 1 deletions
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 87427e4..b9b9a71 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -28,7 +28,11 @@ #include <mpc5xxx.h> #include <pci.h> -#include "mt48lc8m32b2-6-7.h" +/* Two MT48LC8M32B2 for 32 MB */ +/* #include "mt48lc8m32b2-6-7.h" */ + +/* One MT48LC16M32S2 for 64 MB */ +#include "mt48lc16m32s2-75.h" DECLARE_GLOBAL_DATA_PTR; @@ -74,6 +78,8 @@ static void sdram_start (int hi_addr) /* normal operation */ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; __asm__ volatile ("sync"); + + udelay(10); } #endif diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/mcc200/mt48lc16m32s2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif |