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-rw-r--r--board/lwmon5/lwmon5.c10
-rw-r--r--board/lwmon5/sdram.c22
2 files changed, 16 insertions, 16 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 69b45ac..b303ec7 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -34,9 +34,9 @@ int board_early_init_f(void)
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
- /* PLB Write pipelining disabled. Denali Core workaround */
- mtdcr(plb0_acr, 0xDE000000);
- mtdcr(plb1_acr, 0xDE000000);
+ /* PLB Write pipelining disabled. Denali Core workaround */
+ mtdcr(plb0_acr, 0xDE000000);
+ mtdcr(plb1_acr, 0xDE000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@@ -86,9 +86,9 @@ int board_early_init_f(void)
mtsdr(SDR0_PFC4, 0x80000000);
/* PCI arbiter disabled */
- /* PCI Host Configuration disbaled */
+ /* PCI Host Configuration disbaled */
mfsdr(sdr_pci0, reg);
- reg = 0;
+ reg = 0;
mtsdr(sdr_pci0, 0x00000000 | reg);
gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index d2eb5bd..85811ad 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -1,10 +1,10 @@
/*
* (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -49,9 +49,9 @@
* everything correctly.
*/
#ifdef CFG_ENABLE_SDRAM_CACHE
-#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
@@ -325,8 +325,8 @@ void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
- debug("wr_dqs_shift = %d\n", wr_dqs_shift);
- debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
+ debug("wr_dqs_shift = %d\n", wr_dqs_shift);
+ debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
@@ -561,16 +561,16 @@ long int initdram (int board_type)
wait_for_dlllock();
- /*
+ /*
* Program tlb entries for this size (dynamic)
*/
- program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
+ program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
/*
* Setup 2nd TLB with same physical address but different virtual address
* with cache enabled. This is done for fast ECC generation.
*/
- program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+ program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#ifdef CONFIG_DDR_DATA_EYE
/*