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-rw-r--r--board/kup4k/flash.c13
-rw-r--r--board/kup4k/kup4k.c463
-rw-r--r--board/kup4k/s1d13706.h114
3 files changed, 303 insertions, 287 deletions
diff --git a/board/kup4k/flash.c b/board/kup4k/flash.c
index 7297c15..619ccb9 100644
--- a/board/kup4k/flash.c
+++ b/board/kup4k/flash.c
@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = value|(value<<16);
switch (value) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
diff --git a/board/kup4k/kup4k.c b/board/kup4k/kup4k.c
index aeafa6a..b3ede17 100644
--- a/board/kup4k/kup4k.c
+++ b/board/kup4k/kup4k.c
@@ -54,10 +54,7 @@ const uint sdram_table[] =
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
- 0x1F07FC04,
- 0xEEAEFC04,
- 0x11ADFC04,
- 0xEFBBBC00,
+ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0x1FF77C47, /* last */
/*
@@ -68,57 +65,37 @@ const uint sdram_table[] =
* sequence, which is executed by a RUN command.
*
*/
- 0x1FF77C35,
- 0xEFEABC34,
- 0x1FB57C35, /* last */
+ 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
- 0x1F07FC04,
- 0xEEAEFC04,
- 0x10ADFC04,
- 0xF0AFFC00,
- 0xF0AFFC00,
- 0xF1AFFC00,
- 0xEFBBBC00,
- 0x1FF77C47, /* last */
+ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0x1F27FC04,
- 0xEEAEBC00,
- 0x01B93C04,
- 0x1FF77C47, /* last */
+ 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
- 0x1F07FC04,
- 0xEEAEBC00,
- 0x10AD7C00,
- 0xF0AFFC00,
- 0xF0AFFC00,
- 0xE1BBBC04,
- 0x1FF77C47, /* last */
- _NOT_USED_,
+ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+ 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
- 0x1FF5FC84,
- 0xFFFFFC04,
- 0xFFFFFC04,
- 0xFFFFFC04,
- 0xFFFFFC84,
- 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
@@ -146,89 +123,96 @@ int checkboard (void)
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0 = 0;
- long int size_b1 = 0;
- long int size_b2 = 0;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CFG_MPTPR;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
-/* memctl->memc_or1 = CFG_OR1_PRELIM; */
-/* memctl->memc_br1 = CFG_BR1_PRELIM; */
-
-/* memctl->memc_or2 = CFG_OR2_PRELIM; */
-/* memctl->memc_br2 = CFG_BR2_PRELIM; */
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0 = 0;
+ long int size_b1 = 0;
+ long int size_b2 = 0;
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR;
- udelay(200);
+ memctl->memc_mar = 0x00000088;
- /* perform SDRAM initializsation sequence */
+ /*
+ * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+/* memctl->memc_or1 = CFG_OR1_PRELIM; */
+/* memctl->memc_br1 = CFG_BR1_PRELIM; */
+
+/* memctl->memc_or2 = CFG_OR2_PRELIM; */
+/* memctl->memc_br2 = CFG_BR2_PRELIM; */
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
- udelay(1);
- memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
- udelay(1);
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
- udelay(1);
- memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
- udelay(1);
- memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
- udelay(1);
+ memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
- memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
- udelay(1);
- memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
- udelay(1);
- memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
- udelay(1);
+ udelay (200);
+ /* perform SDRAM initializsation sequence */
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+ memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
+ udelay (1);
+ memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
+ udelay (1);
- udelay (1000);
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
+ udelay (1);
+ memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
+ udelay (1);
+ memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
+ udelay (1);
- size_b0 = 0x00800000;
- size_b1 = 0x00800000;
- size_b2 = 0x00800000;
+ memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
+ udelay (1);
+ memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
+ udelay (1);
+ memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+ udelay (1);
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+ udelay (1000);
+#if 0 /* 3 x 8MB */
+ size_b0 = 0x00800000;
+ size_b1 = 0x00800000;
+ size_b2 = 0x00800000;
memctl->memc_mptpr = CFG_MPTPR;
- udelay(1000);
-
+ udelay (1000);
memctl->memc_or1 = 0xFF800A00;
memctl->memc_br1 = 0x00000081;
-
- memctl->memc_or2 = 0xFF000A00;
- memctl->memc_br2 = 0x00800081;
-
+ memctl->memc_or2 = 0xFF000A00;
+ memctl->memc_br2 = 0x00800081;
memctl->memc_or3 = 0xFE000A00;
memctl->memc_br3 = 0x01000081;
+#else /* 3 x 16 MB */
+ size_b0 = 0x01000000;
+ size_b1 = 0x01000000;
+ size_b2 = 0x01000000;
+ memctl->memc_mptpr = CFG_MPTPR;
+ udelay (1000);
+ memctl->memc_or1 = 0xFF000A00;
+ memctl->memc_br1 = 0x00000081;
+ memctl->memc_or2 = 0xFE000A00;
+ memctl->memc_br2 = 0x01000081;
+ memctl->memc_or3 = 0xFC000A00;
+ memctl->memc_br3 = 0x02000081;
+#endif
- udelay(10000);
-
+ udelay (10000);
- return (size_b0 + size_b1 + size_b2);
+ return (size_b0 + size_b1 + size_b2);
}
/* ------------------------------------------------------------------------- */
@@ -241,46 +225,47 @@ long int initdram (int board_type)
* - short between data lines
*/
#if 0
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ ulong cnt, val;
+ ulong save[32]; /* to make test non-destructive */
+ unsigned char i = 0;
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ memctl->memc_mamr = mamr_value;
- val = *addr;
- *addr = save[--i];
+ for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
+ save[i++] = *addr;
+ *addr = ~cnt;
}
- }
- return (maxsize);
+
+ /* write 0 to base address */
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+ *addr = save[--i];
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof (long));
+ }
+ }
+ return (maxsize);
}
#endif
@@ -289,155 +274,175 @@ int misc_init_r (void)
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_STATUS_LED
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
#endif
#ifdef CONFIG_KUP4K_LOGO
bd_t *bd = gd->bd;
- lcd_logo(bd);
-#endif /* CONFIG_KUP4K_LOGO */
+ lcd_logo (bd);
+#endif /* CONFIG_KUP4K_LOGO */
#ifdef CONFIG_IDE_LED
/* Configure PA8 as output port */
immap->im_ioport.iop_padir |= 0x80;
immap->im_ioport.iop_paodr |= 0x80;
immap->im_ioport.iop_papar &= ~0x80;
- immap->im_ioport.iop_padat |= 0x80; /* turn it off */
+ immap->im_ioport.iop_padat |= 0x80; /* turn it off */
#endif
- return(0);
+ return (0);
}
#ifdef CONFIG_KUP4K_LOGO
-void lcd_logo(bd_t *bd){
- FB_INFO_S1D13xxx fb_info;
- S1D_INDEX s1dReg;
- S1D_VALUE s1dValue;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl;
+
+#define PB_LCD_PWM ((uint)0x00004000) /* PB 17 */
+
+void lcd_logo (bd_t * bd)
+{
+
+
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+
+
+ FB_INFO_S1D13xxx fb_info;
+ S1D_INDEX s1dReg;
+ S1D_VALUE s1dValue;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl;
ushort i;
uchar *fb;
- int rs, gs, bs;
- int r = 8, g = 8, b = 4;
- int r1,g1,b1;
+ int rs, gs, bs;
+ int r = 8, g = 8, b = 4;
+ int r1, g1, b1;
+
+ immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM;
+ immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM;
+ immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM; /* set to 0 = enabled */
+ immr->im_cpm.cp_pbdir |= PB_LCD_PWM;
+
/*----------------------------------------------------------------------------- */
-/**/
+ /**/
/* Initialize the chip and the frame buffer driver. */
-/**/
+ /**/
/*----------------------------------------------------------------------------- */
- memctl = &immr->im_memctl;
+ memctl = &immr->im_memctl;
/* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
/* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
- memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
- memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
+ memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
+ memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
- fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
- fb_info.RegAddr = (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
+ fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
+ fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
- if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
- {
- printf("Warning:LCD Controller S1D13706 not found\n");
- return;
- }
+ if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
+ || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
+ printf ("Warning:LCD Controller S1D13706 not found\n");
+ return;
+ }
- /* init controller */
- for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
- {
- s1dReg = aS1DRegs[i].Index;
- s1dValue = aS1DRegs[i].Value;
+ /* init controller */
+ for (i = 0; i < sizeof (aS1DRegs) / sizeof (aS1DRegs[0]); i++) {
+ s1dReg = aS1DRegs[i].Index;
+ s1dValue = aS1DRegs[i].Value;
/* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
- ((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
- }
+ ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
+ s1dValue;
+ }
#undef MONOCHROME
#ifdef MONOCHROME
- switch(bd->bi_busfreq){
+ switch (bd->bi_busfreq) {
#if 0
- case 24000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
- break;
- case 32000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
- break;
+ case 24000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x28;
+ break;
+ case 32000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x33;
+ break;
#endif
- case 40000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
- break;
- case 48000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
- break;
- default:
- printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
- case 64000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
- break;
+ case 40000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x40;
+ break;
+ case 48000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x4C;
+ break;
+ default:
+ printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
+ bd->bi_busfreq);
+ case 64000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x69;
+ break;
}
- ((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x10] = 0x00;
#else
- switch(bd->bi_busfreq){
+ switch (bd->bi_busfreq) {
#if 0
- case 24000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
- break;
- case 32000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
- break;
+ case 24000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+ break;
+ case 32000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+ break;
#endif
- case 40000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
- break;
- case 48000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
- break;
- default:
- printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
- case 64000000:
- ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
- ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
- break;
+ case 40000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
+ break;
+ case 48000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+ break;
+ default:
+ printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
+ bd->bi_busfreq);
+ case 64000000:
+ ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
+ break;
}
#endif
-
- /* create and set colormap */
- rs = 256 / (r - 1);
- gs = 256 / (g - 1);
- bs = 256 / (b - 1);
- for(i=0;i<256;i++){
- r1=(rs * ((i / (g * b)) % r)) * 255;
- g1=(gs * ((i / b) % g)) * 255;
- b1=(bs * ((i) % b)) * 255;
+
+ /* create and set colormap */
+ rs = 256 / (r - 1);
+ gs = 256 / (g - 1);
+ bs = 256 / (b - 1);
+ for (i = 0; i < 256; i++) {
+ r1 = (rs * ((i / (g * b)) % r)) * 255;
+ g1 = (gs * ((i / b) % g)) * 255;
+ b1 = (bs * ((i) % b)) * 255;
/* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
- S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
- }
+ S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
+ (b1 >> 4));
+ }
- /* copy bitmap */
- fb = (char *) (fb_info.VmemAddr);
- memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
+ /* copy bitmap */
+ fb = (char *) (fb_info.VmemAddr);
+ memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
}
-#endif /* CONFIG_KUP4K_LOGO */
+#endif /* CONFIG_KUP4K_LOGO */
#ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
/* We have one led for both pcmcia slots */
- if (status) { /* led on */
+ if (status) { /* led on */
immap->im_ioport.iop_padat &= ~0x80;
} else {
immap->im_ioport.iop_padat |= 0x80;
diff --git a/board/kup4k/s1d13706.h b/board/kup4k/s1d13706.h
index 4eeea39..90027bf 100644
--- a/board/kup4k/s1d13706.h
+++ b/board/kup4k/s1d13706.h
@@ -50,66 +50,64 @@ typedef struct
static S1D_REGS aS1DRegs[] =
{
-
-
- {0x04,0x10}, /* BUSCLK MEMCLK Config Register */
+ {0x04,0x10}, /* BUSCLK MEMCLK Config Register */
#if 0
- {0x05,0x32}, /* PCLK Config Register */
+ {0x05,0x32}, /* PCLK Config Register */
#endif
- {0x10,0xD0}, /* PANEL Type Register */
- {0x11,0x00}, /* MOD Rate Register */
+ {0x10,0xD0}, /* PANEL Type Register */
+ {0x11,0x00}, /* MOD Rate Register */
#if 0
- {0x12,0x34}, /* Horizontal Total Register */
+ {0x12,0x34}, /* Horizontal Total Register */
#endif
- {0x14,0x27}, /* Horizontal Display Period Register */
- {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
- {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
- {0x18,0xF0}, /* Vertical Total Register 0 */
- {0x19,0x00}, /* Vertical Total Register 1 */
- {0x1C,0xEF}, /* Vertical Display Period Register 0 */
- {0x1D,0x00}, /* Vertical Display Period Register 1 */
- {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
- {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
- {0x20,0x87}, /* Horizontal Sync Pulse Width Register */
- {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
- {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
- {0x24,0x80}, /* Vertical Sync Pulse Width Register */
- {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
- {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
- {0x70,0x83}, /* Display Mode Register */
- {0x71,0x00}, /* Special Effects Register */
- {0x74,0x00}, /* Main Window Display Start Address Register 0 */
- {0x75,0x00}, /* Main Window Display Start Address Register 1 */
- {0x76,0x00}, /* Main Window Display Start Address Register 2 */
- {0x78,0x50}, /* Main Window Address Offset Register 0 */
- {0x79,0x00}, /* Main Window Address Offset Register 1 */
- {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
- {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
- {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
- {0x80,0x50}, /* Sub Window Address Offset Register 0 */
- {0x81,0x00}, /* Sub Window Address Offset Register 1 */
- {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
- {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
- {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
- {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
- {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
- {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
- {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
- {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
- {0xA0,0x00}, /* Power Save Config Register */
- {0xA1,0x00}, /* CPU Access Control Register */
- {0xA2,0x00}, /* Software Reset Register */
- {0xA3,0x00}, /* BIG Endian Support Register */
- {0xA4,0x00}, /* Scratch Pad Register 0 */
- {0xA5,0x00}, /* Scratch Pad Register 1 */
- {0xA8,0x01}, /* GPIO Config Register 0 */
- {0xA9,0x80}, /* GPIO Config Register 1 */
- {0xAC,0x01}, /* GPIO Status Control Register 0 */
- {0xAD,0x00}, /* GPIO Status Control Register 1 */
- {0xB0,0x00}, /* PWM CV Clock Control Register */
- {0xB1,0x00}, /* PWM CV Clock Config Register */
- {0xB2,0x00}, /* CV Clock Burst Length Register */
- {0xB3,0x00}, /* PWM Clock Duty Cycle Register */
- {0xAD,0x80}, /* reset seq */
- {0x70,0x03}, /* */
+ {0x14,0x27}, /* Horizontal Display Period Register */
+ {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
+ {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
+ {0x18,0xF0}, /* Vertical Total Register 0 */
+ {0x19,0x00}, /* Vertical Total Register 1 */
+ {0x1C,0xEF}, /* Vertical Display Period Register 0 */
+ {0x1D,0x00}, /* Vertical Display Period Register 1 */
+ {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
+ {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
+ {0x20,0x87}, /* Horizontal Sync Pulse Width Register */
+ {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
+ {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
+ {0x24,0x80}, /* Vertical Sync Pulse Width Register */
+ {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
+ {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
+ {0x70,0x83}, /* Display Mode Register */
+ {0x71,0x00}, /* Special Effects Register */
+ {0x74,0x00}, /* Main Window Display Start Address Register 0 */
+ {0x75,0x00}, /* Main Window Display Start Address Register 1 */
+ {0x76,0x00}, /* Main Window Display Start Address Register 2 */
+ {0x78,0x50}, /* Main Window Address Offset Register 0 */
+ {0x79,0x00}, /* Main Window Address Offset Register 1 */
+ {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
+ {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
+ {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
+ {0x80,0x50}, /* Sub Window Address Offset Register 0 */
+ {0x81,0x00}, /* Sub Window Address Offset Register 1 */
+ {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
+ {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
+ {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
+ {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
+ {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
+ {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
+ {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
+ {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
+ {0xA0,0x00}, /* Power Save Config Register */
+ {0xA1,0x00}, /* CPU Access Control Register */
+ {0xA2,0x00}, /* Software Reset Register */
+ {0xA3,0x00}, /* BIG Endian Support Register */
+ {0xA4,0x00}, /* Scratch Pad Register 0 */
+ {0xA5,0x00}, /* Scratch Pad Register 1 */
+ {0xA8,0x01}, /* GPIO Config Register 0 */
+ {0xA9,0x80}, /* GPIO Config Register 1 */
+ {0xAC,0x01}, /* GPIO Status Control Register 0 */
+ {0xAD,0x00}, /* GPIO Status Control Register 1 */
+ {0xB0,0x10}, /* PWM CV Clock Control Register */
+ {0xB1,0x80}, /* PWM CV Clock Config Register */
+ {0xB2,0x00}, /* CV Clock Burst Length Register */
+ {0xB3,0xA0}, /* PWM Clock Duty Cycle Register */
+ {0xAD,0x80}, /* reset seq */
+ {0x70,0x03}, /* */
};
generated by cgit v1.1 at 2024-11-23 19:26:56 +0000