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-rw-r--r--board/keymile/common/common.h5
-rw-r--r--board/keymile/km_arm/Makefile4
-rw-r--r--board/keymile/km_arm/fpga_config.c256
-rw-r--r--board/keymile/km_arm/km_arm.c152
-rw-r--r--board/keymile/km_arm/kwbimage-memphis.cfg2
-rw-r--r--board/keymile/km_arm/kwbimage_128M16_1.cfg294
-rw-r--r--board/keymile/km_arm/kwbimage_256M8_1.cfg296
7 files changed, 936 insertions, 73 deletions
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index f457aa3..aab706e 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -131,6 +131,11 @@ struct bfticu_iomap {
int ethernet_present(void);
int ivm_read_eeprom(void);
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
int set_km_env(void);
int fdt_set_node_and_value(void *blob,
char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index aa51255..13d485a 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
+ifdef CONFIG_KM_FPGA_CONFIG
+COBJS += fpga_config.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
new file mode 100644
index 0000000..fcc5fe6
--- /dev/null
+++ b/board/keymile/km_arm/fpga_config.c
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN 39
+
+#define BOCO_ADDR 0x10
+
+#define ID_REG 0x00
+#define BOCO2_ID 0x5b
+
+static int check_boco2(void)
+{
+ int ret;
+ u8 id;
+
+ ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO id !!\n", __func__);
+ return ret;
+ }
+
+ return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+ regval &= ~flags;
+ ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+ if (ret) {
+ printf("%s: error writing the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+ regval |= flags;
+ ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+ if (ret) {
+ printf("%s: error writing the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+#define SPI_REG 0x06
+#define CFG_EEPROM 0x02
+#define FPGA_PROG 0x04
+#define FPGA_INIT_B 0x10
+#define FPGA_DONE 0x20
+
+static int fpga_done(void)
+{
+ int ret = 0;
+ u8 regval;
+
+ /* this is only supported with the boco2 design */
+ if (!check_boco2())
+ return 0;
+
+ ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &regval, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, SPI_REG);
+ return 0;
+ }
+
+ return regval & FPGA_DONE ? 1 : 0;
+}
+
+int skip;
+
+int trigger_fpga_config(void)
+{
+ int ret = 0;
+
+ /* if the FPGA is already configured, we do not want to
+ * reconfigure it */
+ skip = 0;
+ if (fpga_done()) {
+ printf("PCIe FPGA config: skipped\n");
+ skip = 1;
+ return 0;
+ }
+
+ if (check_boco2()) {
+ /* we have a BOCO2, this has to be triggered here */
+
+ /* make sure the FPGA_can access the EEPROM */
+ ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
+ if (ret)
+ return ret;
+
+ /* trigger the config start */
+ ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
+ if (ret)
+ return ret;
+
+ /* small delay for the pulse */
+ udelay(10);
+
+ /* up signal for pulse end */
+ ret = boco_set_bits(SPI_REG, FPGA_PROG);
+ if (ret)
+ return ret;
+
+ /* finally, raise INIT_B to remove the config delay */
+ ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
+ if (ret)
+ return ret;
+
+ } else {
+ /* we do it the old way, with the gpio pin */
+ kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+ kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+ /* small delay for the pulse */
+ udelay(10);
+ kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+ }
+
+ return 0;
+}
+
+int wait_for_fpga_config(void)
+{
+ int ret = 0;
+ u8 spictrl;
+ u32 timeout = 20000;
+
+ if (skip)
+ return 0;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ printf("PCIe FPGA config:");
+ do {
+ ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO spictrl !!\n",
+ __func__);
+ return ret;
+ }
+ if (timeout-- == 0) {
+ printf(" FPGA_DONE timeout\n");
+ return -EFAULT;
+ }
+ udelay(10);
+ } while (!(spictrl & FPGA_DONE));
+
+ printf(" done\n");
+
+ return 0;
+}
+
+#define PRST1 0x4
+#define PCIE_RST 0x10
+#define TRAFFIC_RST 0x04
+
+int fpga_reset(void)
+{
+ int ret = 0;
+ u8 resets;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ /* if we have skipped, we only want to reset the PCIe part */
+ resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+ ret = boco_clear_bits(PRST1, resets);
+ if (ret)
+ return ret;
+
+ /* small delay for the pulse */
+ udelay(10);
+
+ ret = boco_set_bits(PRST1, resets);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
+ * is available from the Bobcat SPI bus */
+int toggle_eeprom_spi_bus(void)
+{
+ int ret = 0;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ ret = boco_set_bits(SPI_REG, CFG_EEPROM);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 9e9940c..2b2ca39 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -33,6 +33,7 @@
#include <nand.h>
#include <netdev.h>
#include <miiphy.h>
+#include <spi.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
@@ -113,7 +114,7 @@ u32 kwmpp_config[] = {
0
};
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
/*
* Wait for startup OK from mgcoge3ne
*/
@@ -133,10 +134,10 @@ int startup_allowed(void)
}
#endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
/*
- * These two boards have always ethernet present. Its connected to the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
*/
int ethernet_present(void)
{
@@ -201,7 +202,7 @@ int misc_init_r(void)
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
gd->bd->bi_arch_number = mach_type;
}
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
char *wait_for_ne;
wait_for_ne = getenv("waitforne");
if (wait_for_ne != NULL) {
@@ -242,90 +243,93 @@ int misc_init_r(void)
int board_early_init_f(void)
{
+#if defined(CONFIG_SOFT_I2C)
u32 tmp;
- kirkwood_mpp_conf(kwmpp_config);
+ /* set the 2 bitbang i2c pins as output gpios */
+ tmp = readl(KW_GPIO0_BASE + 4);
+ writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
/*
- * The FLASH_GPIO_PIN switches between using a
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ /*
+ * The KM_FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+ kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+ kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C)
- /* init the GPIO for I2C Bitbang driver */
+ /*
+ * Reinit the GPIO for I2C Bitbang driver so that the now
+ * available gpio framework is consistent. The calls to
+ * direction output in are not necessary, they are already done in
+ * board_early_init_f
+ */
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
- kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
- kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
#endif
+
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
-#if defined(CONFIG_KM_RECONFIG_XLX)
- /* trigger the reconfiguration of the xilinx fpga */
- kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
- kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
- kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+
+#if defined(CONFIG_KM_FPGA_CONFIG)
+ trigger_fpga_config();
#endif
+
return 0;
}
-int board_init(void)
+int board_late_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+#if defined(CONFIG_KMCOGE5UN)
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE 43
+ u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+ /* if pin 1 do full erase */
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
+#if defined(CONFIG_KM_FPGA_CONFIG)
+ wait_for_fpga_config();
+ fpga_reset();
+ toggle_eeprom_spi_bus();
+#endif
return 0;
}
-#if defined(CONFIG_CMD_SF)
-int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int board_spi_claim_bus(struct spi_slave *slave)
{
- u32 tmp;
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if ((strcmp(argv[1], "off") == 0)) {
- printf("SPI FLASH disabled, NAND enabled\n");
- /* Multi-Purpose Pins Functionality configuration */
- kwmpp_config[0] = MPP0_NF_IO2;
- kwmpp_config[1] = MPP1_NF_IO3;
- kwmpp_config[2] = MPP2_NF_IO4;
- kwmpp_config[3] = MPP3_NF_IO5;
-
- kirkwood_mpp_conf(kwmpp_config);
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- } else if ((strcmp(argv[1], "on") == 0)) {
- printf("SPI FLASH enabled, NAND disabled\n");
- /* Multi-Purpose Pins Functionality configuration */
- kwmpp_config[0] = MPP0_SPI_SCn;
- kwmpp_config[1] = MPP1_SPI_MOSI;
- kwmpp_config[2] = MPP2_SPI_SCK;
- kwmpp_config[3] = MPP3_SPI_MISO;
-
- kirkwood_mpp_conf(kwmpp_config);
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
- } else {
- return cmd_usage(cmdtp);
- }
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
return 0;
}
-U_BOOT_CMD(
- spitoggle, 2, 0, do_spi_toggle,
- "En-/disable SPI FLASH access",
- "<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
- );
-#endif
+void board_spi_release_bus(struct spi_slave *slave)
+{
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+}
int dram_init(void)
{
@@ -347,15 +351,15 @@ void dram_init_banksize(void)
}
}
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
-#define PHY_LED_SEL 0x18
-#define PHY_LED0_LINK (0x5)
-#define PHY_LED1_ACT (0x8<<4)
-#define PHY_LED2_INT (0xe<<8)
-#define PHY_SPEC_CTRL 0x1c
+#define PHY_LED_SEL_REG 0x18
+#define PHY_LED0_LINK (0x5)
+#define PHY_LED1_ACT (0x8<<4)
+#define PHY_LED2_INT (0xe<<8)
+#define PHY_SPEC_CTRL_REG 0x1c
#define PHY_RGMII_CLK_STABLE (0x1<<10)
-#define PHY_CLSA (0x1<<1)
+#define PHY_CLSA (0x1<<1)
/* Configure and enable MV88E3018 PHY */
void reset_phy(void)
@@ -367,15 +371,15 @@ void reset_phy(void)
return;
/* RGMII clk transition on data stable */
- if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0)
+ if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
printf("Error reading PHY spec ctrl reg\n");
- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
- reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
+ if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+ reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
printf("Error writing PHY spec ctrl reg\n");
/* leds setup */
- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
- PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
+ if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+ PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
printf("Error writing PHY LED reg\n");
/* reset the phy */
@@ -410,7 +414,7 @@ const ulong patterns[] = { 0x00000000,
0xFF00FF00,
0x0F0F0F0F,
0xF0F0F0F0};
-const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns);
+const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
const ulong OFFS_PATTERN = 3;
const ulong REPEAT_PATTERN = 1000;
@@ -486,7 +490,11 @@ int get_scl(void)
int post_hotkeys_pressed(void)
{
+#if defined(CONFIG_KM_COGE5UN)
+ return kw_gpio_get_value(KM_POST_EN_L);
+#else
return !kw_gpio_get_value(KM_POST_EN_L);
+#endif
}
ulong post_word_load(void)
diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg
index 2faaf2b..6df2ad7 100644
--- a/board/keymile/km_arm/kwbimage-memphis.cfg
+++ b/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -149,7 +149,7 @@ DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
# bit3-0 : 0000, required
# bit7-4 : 0010, M_ODT assertion 2 cycles after read
-# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read
+# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
# bit15-12: 0100, internal ODT assertion 4 cycles after read
# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
# bit31-20: 0 , required
diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg
new file mode 100644
index 0000000..bcce907
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -0,0 +1,294 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
+# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
+# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4 NF_IO[6]
+# bit 23-20: 1, MPPSel5 NF_IO[7]
+# bit 27-24: 1, MPPSel6 SYSRST_O
+# bit 31-28: 0, MPPSel7 GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0: 0, MPPSel8 GPIO[8]
+# bit 7-4: 0, MPPSel9 GPIO[9]
+# bit 12-8: 3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: 0, MPPSel16 GPIO[16]
+# bit 7-4: 0, MPPSel17 not connected
+# bit 12-8: 1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+# bit 2-0: 3, Reserved
+# bit 5-3: 3, Reserved
+# bit 6: 0, Reserved
+# bit 7: 0, RGMII-pads voltage = 3.3V
+# bit 10-8: 3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14: 0, Reserved
+# bit 15: 0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16 0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+# bit 0-1: 2, Tag RAM RTC RAM0
+# bit 3-2: 1, Tag RAM WTC RAM0
+# bit 7-4: 6, Reserve
+# bit 9-8: 2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+# bit 15-0: ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
+# bit 23-0: 0x000200, Addr Config tuning
+# bit 31-24: 0, Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
+# bit 15-0: 0x1C00, Opmux Tuning
+# bit 31-16: 0, Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
+# bit 1-0: 1, addr clk tune
+# bit 3-2: 0, reserved
+# bit 5-4: 0, dtcmp clk tune
+# bit 7-6: 0, reserved
+# bit 9-8: 0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
+# bit 13-0: 0x4E0, DDR2 clks refresh rate
+# bit 14: 0, reserved
+# bit 15: 0, reserved
+# bit 16: 0, CPU to Dram Write buffer policy
+# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24: 1, enable exit self refresh mode on DDR access
+# bit 25: 1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 3-0: 0, reserved
+# bit 4: 0, 2T mode =addr/cmd in same cycle
+# bit 5: 0, clk is driven during self refresh, we don't care for APX
+# bit 6: 0, use recommended falling edge of clk for addr/cmd
+# bit 7-11: 0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14: 0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18: 1, cpu lock transaction enabled
+# bit 19: 0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
+# bit 30-28: 3, required
+# bit 31: 0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
+# bit 3-0: 0xE, TRAS, 15 clk (45 ns)
+# bit 7-4: 0x4, TRCD, 5 clk (15 ns)
+# bit 11-8: 0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20: 0, extended TRAS msb
+# bit 23-21: 0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
+# bit 6-0: 0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7: 0, TR2R
+# bit 10-9: 0, TR2W
+# bit 12-11: 0, TW2W
+# bit 31-13: 0, reserved
+
+DATA 0xFFD01410 0x00000001 # DDR Address Control
+# bit 1-0: 1, Cs0width=x16
+# bit 3-2: 0, Cs0size=2Gb
+# bit 5-4: 0, Cs1width=nonexistent
+# bit 7-6: 0, Cs1size =nonexistent
+# bit 9-8: 0, Cs2width=nonexistent
+# bit 11-10: 0, Cs2size =nonexistent
+# bit 13-12: 0, Cs3width=nonexistent
+# bit 15-14: 0, Cs3size =nonexistent
+# bit 16: 0, Cs0AddrSel
+# bit 17: 0, Cs1AddrSel
+# bit 18: 0, Cs2AddrSel
+# bit 19: 0, Cs3AddrSel
+# bit 31-20: 0, required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit 0: 0, OpenPage enabled
+# bit 31-1: 0, required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit 3-0: 0, DDR cmd
+# bit 31-4: 0, required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit 2-0: 2, Burst Length = 4
+# bit 3: 0, Burst Type
+# bit 6-4: 5, CAS Latency = 5
+# bit 7: 0, Test mode
+# bit 8: 0, DLL Reset
+# bit 11-9: 3, Write recovery for auto-precharge must be 3
+# bit 12: 0, Active power down exit time, fast exit
+# bit 14-13: 0, reserved
+# bit 31-15: 0, reserved
+
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode
+# bit 0: 0, DDR DLL enabled
+# bit 1: 1, DDR drive strength reduced
+# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3: 0, required
+# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7: 0, required
+# bit 10: 0, differential DQS enabled
+# bit 11: 0, required
+# bit 12: 0, DDR output buffer enabled
+# bit 31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit 2-0: 7, required
+# bit 3: 1, MBUS Burst Chop disabled
+# bit 6-4: 7, required
+# bit 7: 0, reserved
+# bit 8: 1, add sample stage required for f > 266 MHz
+# bit 9: 0, no half clock cycle addition to dataout
+# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16: 0, required
+
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
+# bit 3-0: 0, required
+# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
+# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
+# (ODT turn off delay 2,5 clk cycles)
+# bit 15-12: 4, internal ODT time based on bit 7-4
+# with the considered SDRAM internal delay
+# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
+# with the considered SDRAM internal delay
+# bit 31-20: 0, required
+
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
+# bit 3-0: 2, M_ODT assertion same as bit 11-8
+# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
+# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
+# with the considered SDRAM internal delay
+# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
+# with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit 23-0: 0, reserved
+# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit 0: 1, Window enabled
+# bit 1: 0, Write Protect disabled
+# bit 3-2: 0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
+# bit 11-8: 0, required
+# big 15-11: 0, required
+# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
+# bit 27-24: 0, required
+# bit 31-28: 0, required
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2: 0, ODT1 controlled by register
+# bit 31-4: 0, required
+
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
+# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM
+# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14: 1, STARTBURST ODT enabled
+# bit 15: 1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit 0: 1, enable DDR init upon this register write
+# bit 31-1: 0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg
new file mode 100644
index 0000000..3e1237b
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -0,0 +1,296 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+# MT47H256M8EB-3IT:C
+# MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
+# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
+# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4 NF_IO[6]
+# bit 23-20: 1, MPPSel5 NF_IO[7]
+# bit 27-24: 1, MPPSel6 SYSRST_O
+# bit 31-28: 0, MPPSel7 GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
+# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
+# bit 12-8: 3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: 0, MPPSel16 GPIO[16]
+# bit 7-4: 0, MPPSel17 not connected
+# bit 11-8: 1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+# bit 2-0: 3, Reserved
+# bit 5-3: 3, Reserved
+# bit 6: 0, Reserved
+# bit 7: 0, RGMII-pads voltage = 3.3V
+# bit 10-8: 3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14: 0, Reserved
+# bit 15: 0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16 0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+# bit 0-1: 2, Tag RAM RTC RAM0
+# bit 3-2: 1, Tag RAM WTC RAM0
+# bit 7-4: 6, Reserved
+# bit 9-8: 2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+# bit 15-0: ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
+# bit 23-0: 0x000200, Addr Config tuning
+# bit 31-24: 0, Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
+# bit 15-0: 0x1C00, Opmux Tuning
+# bit 31-16: 0, Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
+# bit 1-0: 1, addr clk tune
+# bit 3-2: 0, reserved
+# bit 5-4: 0, dtcmp clk tune
+# bit 7-6: 0, reserved
+# bit 9-8: 0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
+# bit 13-0: 0x4E0, DDR2 clks refresh rate
+# bit 14: 0, reserved
+# bit 15: 0, reserved
+# bit 16: 0, CPU to Dram Write buffer policy
+# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24: 1, enable exit self refresh mode on DDR access
+# bit 25: 1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 3-0: 0, reserved
+# bit 4: 0, 2T mode =addr/cmd in same cycle
+# bit 5: 0, clk is driven during self refresh, we don't care for APX
+# bit 6: 0, use recommended falling edge of clk for addr/cmd
+# bit 7-11: 0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14: 0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18: 1, cpu lock transaction enabled
+# bit 19: 0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
+# bit 30-28: 3, required
+# bit 31: 0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
+# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20: 0, extended TRAS msb
+# bit 23-21: 0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
+# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7: 0, TR2R
+# bit 10-9: 0, TR2W
+# bit 12-11: 0, TW2W
+# bit 31-13: 0, reserved
+
+DATA 0xFFD01410 0x00000000 # DDR Address Control
+# bit 1-0: 0, Cs0width=x8 (2 devices)
+# bit 3-2: 0, Cs0size=2Gb
+# bit 5-4: 0, Cs1width=nonexistent
+# bit 7-6: 0, Cs1size =nonexistent
+# bit 9-8: 0, Cs2width=nonexistent
+# bit 11-10: 0, Cs2size =nonexistent
+# bit 13-12: 0, Cs3width=nonexistent
+# bit 15-14: 0, Cs3size =nonexistent
+# bit 16: 0, Cs0AddrSel
+# bit 17: 0, Cs1AddrSel
+# bit 18: 0, Cs2AddrSel
+# bit 19: 0, Cs3AddrSel
+# bit 31-20: 0, required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit 0: 0, OpenPage enabled
+# bit 31-1: 0, required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit 3-0: 0, DDR cmd
+# bit 31-4: 0, required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit 2-0: 2, Burst Length = 4
+# bit 3: 0, Burst Type
+# bit 6-4: 5, CAS Latency = 5
+# bit 7: 0, Test mode
+# bit 8: 0, DLL Reset
+# bit 11-9: 3, Write recovery for auto-precharge must be 3
+# bit 12: 0, Active power down exit time, fast exit
+# bit 14-13: 0, reserved
+# bit 31-15: 0, reserved
+
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode
+# bit 0: 0, DDR DLL enabled
+# bit 1: 1, DDR drive strenght reduced
+# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3: 0, required
+# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7: 0, required
+# bit 10: 0, differential DQS enabled
+# bit 11: 0, required
+# bit 12: 0, DDR output buffer enabled
+# bit 31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit 2-0: 7, required
+# bit 3: 1, MBUS Burst Chop disabled
+# bit 6-4: 7, required
+# bit 7: 0, reserved
+# bit 8: 1, add sample stage required for > 266Mhz
+# bit 9: 0, no half clock cycle addition to dataout
+# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16: 0, required
+
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
+# bit 3-0: 0, required
+# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
+# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
+# (ODT turn off delay 2,5 clk cycles)
+# bit 15-12: 4, internal ODT time based on bit 7-4
+# with the considered SDRAM internal delay
+# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
+# with the considered SDRAM internal delay
+# bit 31-20: 0, required
+
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
+# bit 3-0: 2, M_ODT assertion same as bit 11-8
+# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
+# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
+# with the considered SDRAM internal delay
+# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
+# with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit 23-0: 0, reserved
+# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+# bit 0: 1, Window enabled
+# bit 1: 0, Write Protect disabled
+# bit 3-2: 0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
+# bit 11-8: 0, required
+# big 15-11: 0, required
+# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
+# bit 27-24: 0, required
+# bit 31-28: 0, required
+
+DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
+# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2: 1, ODT1 never active
+# bit 31-4: 0, required
+
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
+# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14: 1, STARTBURST ODT enabled
+# bit 15: 1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit 0: 1, enable DDR init upon this register write
+# bit 31-1: 0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
generated by cgit v1.1 at 2024-11-06 08:08:55 +0000