diff options
Diffstat (limited to 'board/keymile/km_arm')
| -rw-r--r-- | board/keymile/km_arm/km_arm.c | 108 | ||||
| -rw-r--r-- | board/keymile/km_arm/kwbimage-memphis.cfg | 197 |
2 files changed, 278 insertions, 27 deletions
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index c772ee2..d86acc9 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -41,6 +41,16 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * BOCO FPGA definitions + */ +#define BOCO 0x10 +#define REG_CTRL_H 0x02 +#define MASK_WRL_UNITRUN 0x01 +#define MASK_RBX_PGY_PRESENT 0x40 +#define REG_IRQ_CIRQ2 0x2d +#define MASK_RBI_DEFECT_16 0x01 + /* Multi-Purpose Pins Functionality configuration */ u32 kwmpp_config[] = { MPP0_NF_IO2, @@ -102,68 +112,119 @@ u32 kwmpp_config[] = { 0 }; +#if defined(CONFIG_MGCOGE3UN) +/* + * Wait for startup OK from mgcoge3ne + */ +int startup_allowed(void) +{ + unsigned char buf; + + /* + * Read CIRQ16 bit (bit 0) + */ + if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) + printf("%s: Error reading Boco\n", __func__); + else + if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) + return 1; + return 0; +} + +/* + * mgcoge3un has always ethernet present. Its connected to the 6061 switch + * and provides ICNev and piggy4 connections. + */ +int ethernet_present(void) +{ + return 1; +} +#else int ethernet_present(void) { uchar buf; int ret = 0; - if (i2c_read(0x10, 2, 1, &buf, 1) != 0) { + if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { printf("%s: Error reading Boco\n", __func__); return -1; } - if ((buf & 0x40) == 0x40) + if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) ret = 1; return ret; } +#endif int initialize_unit_leds(void) { /* - * init the unit LEDs - * per default they all are + * Init the unit LEDs per default they all are * ok apart from bootstat - * LED connected through BOCO - * BOCO lies at the address 0x10 - * LEDs are in the block CTRL_H (addr 0x02) - * BOOTSTAT LED is the first 0x01 */ - #define BOCO 0x10 - #define CTRL_H 0x02 - #define APPLEDMASK 0x01 uchar buf; - if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) { + if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { printf("%s: Error reading Boco\n", __func__); return -1; } - buf |= APPLEDMASK; - if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) { + buf |= MASK_WRL_UNITRUN; + if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { printf("%s: Error writing Boco\n", __func__); return -1; } return 0; } +#if defined(CONFIG_BOOTCOUNT_LIMIT) +void set_bootcount_addr(void) +{ + uchar buf[32]; + unsigned int bootcountaddr; + bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; + sprintf((char *)buf, "0x%x", bootcountaddr); + setenv("bootcountaddr", (char *)buf); +} +#endif + int misc_init_r(void) { char *str; int mach_type; - puts("Piggy:"); - if (ethernet_present() == 0) - puts (" not"); - puts(" present\n"); - str = getenv("mach_type"); if (str != NULL) { mach_type = simple_strtoul(str, NULL, 10); printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } +#if defined(CONFIG_MGCOGE3UN) + char *wait_for_ne; + wait_for_ne = getenv("waitforne"); + if (wait_for_ne != NULL) { + if (strcmp(wait_for_ne, "true") == 0) { + int cnt = 0; + puts("NE go: "); + while (startup_allowed() == 0) { + udelay(200000); + cnt++; + if (cnt == 5) + puts("wait\b\b\b\b"); + if (cnt == 10) { + cnt = 0; + puts(" \b\b\b\b"); + } + } + puts("OK\n"); + } + } +#endif initialize_unit_leds(); - + set_km_env(); +#if defined(CONFIG_BOOTCOUNT_LIMIT) + set_bootcount_addr(); +#endif return 0; } @@ -182,7 +243,6 @@ int board_early_init_f(void) writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); tmp = readl(KW_GPIO0_BASE + 4); writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); - printf("KM: setting NAND mode\n"); #if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ @@ -212,12 +272,6 @@ int board_init(void) return 0; } -int last_stage_init(void) -{ - set_km_env(); - return 0; -} - #if defined(CONFIG_CMD_SF) int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg new file mode 100644 index 0000000..2faaf2b --- /dev/null +++ b/board/keymile/km_arm/kwbimage-memphis.cfg @@ -0,0 +1,197 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2011 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: MPPSel0 2, NF_IO[2] +# bit 7-4: MPPSel1 2, NF_IO[3] +# bit 12-8: MPPSel2 2, NF_IO[4] +# bit 15-12: MPPSel3 2, NF_IO[5] +# bit 19-16: MPPSel4 1, NF_IO[6] +# bit 23-20: MPPSel5 1, NF_IO[7] +# bit 27-24: MPPSel6 1, SYSRST_O +# bit 31-28: MPPSel7 0, GPO[7] + +DATA 0xFFD10004 0x03303300 + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: MPPSel16 0, GPIO[16] +# bit 7-4: MPPSel17 0, GPIO[17] +# bit 12-8: MPPSel18 1, NF_IO[0] +# bit 15-12: MPPSel19 1, NF_IO[1] +# bit 19-16: MPPSel20 0, GPIO[20] +# bit 23-20: MPPSel21 0, GPIO[21] +# bit 27-24: MPPSel22 0, GPIO[22] +# bit 31-28: MPPSel23 0, GPIO[23] + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +#Dram initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit13-0: 0x4E0 (DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x38543000 # DDR Controller Control Low +# bit 3-0: 0 reserved +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 00, Cs0size=2Gb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd disabled +# bit5-3: 000, required +# bit6: 0, DDR ODT control msb disabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add a sample stage +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit3-0 : 0000, required +# bit7-4 : 0010, M_ODT assertion 2 cycles after read +# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read +# bit15-12: 0100, internal ODT assertion 4 cycles after read +# bit19-16: 1000, internal ODT de-assertion 8 cycles after read +# bit31-20: 0 , required + +DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High +# bit3-0 : 0001, M_ODT assertion same cycle as write +# bit7-4 : 0101, M_ODT de-assertion x cycles after write +# bit11-8 : 0100, internal ODT assertion x cycles after write +# bit15-12: 1000, internal ODT de-assertion x cycles after write + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 00, ODT1 controlled by register +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F801 # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 +# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr +# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm +# bit14 :1, STARTBURST ODT enabled +# bit15 :1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 |