diff options
Diffstat (limited to 'board/isee')
| -rw-r--r-- | board/isee/igep0020/Makefile | 49 | ||||
| -rw-r--r-- | board/isee/igep0020/config.mk | 33 | ||||
| -rw-r--r-- | board/isee/igep0020/igep0020.c | 129 | ||||
| -rw-r--r-- | board/isee/igep0020/igep0020.h | 156 |
4 files changed, 367 insertions, 0 deletions
diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile new file mode 100644 index 0000000..2f11879 --- /dev/null +++ b/board/isee/igep0020/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := igep0020.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk new file mode 100644 index 0000000..b8812f9 --- /dev/null +++ b/board/isee/igep0020/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2009 +# ISEE 2007 SL, <www.iseebcn.com> +# +# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80008000 diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c new file mode 100644 index 0000000..3f7eda1 --- /dev/null +++ b/board/isee/igep0020/igep0020.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2010 + * ISEE 2007 SL, <www.iseebcn.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "igep0020.h" + +/* GPMC definitions for LAN9221 chips */ +static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, +}; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_IGEP0020; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +#if defined(CONFIG_CMD_NET) +static void setup_net_chip(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, + GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 64 as output pin and send a magic pulse through it */ + if (!omap_request_gpio(64)) { + omap_set_gpio_direction(64, 0); + omap_set_gpio_dataout(64, 1); + udelay(1); + omap_set_gpio_dataout(64, 0); + udelay(1); + omap_set_gpio_dataout(64, 1); + } +} +#endif + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + twl4030_power_init(); + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h new file mode 100644 index 0000000..c08d758 --- /dev/null +++ b/board/isee/igep0020/igep0020.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2010 + * ISEE 2007 SL, <www.iseebcn.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _IGEP0020_H_ +#define _IGEP0020_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "IGEP v2 board", + "ONENAND", +}; + +/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00080701 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x08030703 +#define NET_LAN9221_GPMC_CONFIG5 0x00060908 +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + +static void setup_net_chip(void); + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ +#endif |