diff options
Diffstat (limited to 'board/intercontrol')
| -rw-r--r-- | board/intercontrol/digsy_mtc/Makefile | 33 | ||||
| -rw-r--r-- | board/intercontrol/digsy_mtc/cmd_disp.c | 57 | ||||
| -rw-r--r-- | board/intercontrol/digsy_mtc/cmd_mtc.c | 385 | ||||
| -rw-r--r-- | board/intercontrol/digsy_mtc/cmd_mtc.h | 61 | ||||
| -rw-r--r-- | board/intercontrol/digsy_mtc/digsy_mtc.c | 500 | ||||
| -rw-r--r-- | board/intercontrol/digsy_mtc/eeprom.h | 32 | ||||
| -rw-r--r-- | board/intercontrol/digsy_mtc/is42s16800a-7t.h | 27 | ||||
| -rw-r--r-- | board/intercontrol/digsy_mtc/is45s16800a2.h | 31 |
8 files changed, 1126 insertions, 0 deletions
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile new file mode 100644 index 0000000..19f5b3a --- /dev/null +++ b/board/intercontrol/digsy_mtc/Makefile @@ -0,0 +1,33 @@ + +# +# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o cmd_mtc.o +COBJS-$(CONFIG_VIDEO) += cmd_disp.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c new file mode 100644 index 0000000..d5f5efb --- /dev/null +++ b/board/intercontrol/digsy_mtc/cmd_disp.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2011 DENX Software Engineering, + * Anatolij Gustschin <agust@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <mpc5xxx.h> +#include <asm/io.h> + +#define GPIO_USB1_0 0x00010000 + +static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (argc < 2) { + printf("%s\n", + in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off"); + return 0; + } + + if (!strncmp(argv[1], "on", 2)) { + setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); + } else if (!strncmp(argv[1], "off", 3)) { + clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0); + } else { + cmd_usage(cmdtp); + return 1; + } + return 0; +} + +U_BOOT_CMD(disp, 2, 1, cmd_disp, + "disp [on/off] - switch display on/off", + "\n - print display on/off status\n" + "on\n - turn on\n" + "off\n - turn off\n" +); diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.c b/board/intercontrol/digsy_mtc/cmd_mtc.c new file mode 100644 index 0000000..fffcee9 --- /dev/null +++ b/board/intercontrol/digsy_mtc/cmd_mtc.c @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2009 + * Werner Pfister <Pfister_Werner@intercontrol.de> + * + * (C) Copyright 2009 Semihalf, Grzegorz Bernacki + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <mpc5xxx.h> +#include "spi.h" +#include "cmd_mtc.h" + +DECLARE_GLOBAL_DATA_PTR; + +static uchar user_out; + +static const char *led_names[] = { + "diag", + "can1", + "can2", + "can3", + "can4", + "usbpwr", + "usbbusy", + "user1", + "user2", + "" +}; + +static int msp430_xfer(const void *dout, void *din) +{ + int err; + + err = spi_xfer(NULL, MTC_TRANSFER_SIZE, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); + + /* The MSP chip needs time to ready itself for the next command */ + udelay(1000); + + return err; +} + +static void mtc_calculate_checksum(tx_msp_cmd *packet) +{ + int i; + uchar *buff; + + buff = (uchar *) packet; + + for (i = 0; i < 6; i++) + packet->cks += buff[i]; +} + +static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + tx_msp_cmd pcmd; + rx_msp_cmd prx; + int err; + int i; + + if (argc < 2) + return cmd_usage(cmdtp); + + memset(&pcmd, 0, sizeof(pcmd)); + memset(&prx, 0, sizeof(prx)); + + pcmd.cmd = CMD_SET_LED; + + pcmd.cmd_val0 = 0xff; + for (i = 0; strlen(led_names[i]) != 0; i++) { + if (strncmp(argv[1], led_names[i], strlen(led_names[i])) == 0) { + pcmd.cmd_val0 = i; + break; + } + } + + if (pcmd.cmd_val0 == 0xff) { + printf("Usage:\n%s\n", cmdtp->help); + return -1; + } + + if (argc >= 3) { + if (strncmp(argv[2], "red", 3) == 0) + pcmd.cmd_val1 = 1; + else if (strncmp(argv[2], "green", 5) == 0) + pcmd.cmd_val1 = 2; + else if (strncmp(argv[2], "orange", 6) == 0) + pcmd.cmd_val1 = 3; + else + pcmd.cmd_val1 = 0; + } + + if (argc >= 4) + pcmd.cmd_val2 = simple_strtol(argv[3], NULL, 10); + else + pcmd.cmd_val2 = 0; + + pcmd.user_out = user_out; + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + + return err; +} + +static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + tx_msp_cmd pcmd; + rx_msp_cmd prx; + int err; + + memset(&pcmd, 0, sizeof(pcmd)); + memset(&prx, 0, sizeof(prx)); + + pcmd.cmd = CMD_GET_VIM; + pcmd.user_out = user_out; + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + + if (!err) { + /* function returns '0' if key is pressed */ + err = (prx.input & 0x80) ? 0 : 1; + } + + return err; +} + +static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + tx_msp_cmd pcmd; + rx_msp_cmd prx; + int err; + uchar channel_mask = 0; + + if (argc < 3) + return cmd_usage(cmdtp); + + if (strncmp(argv[1], "on", 2) == 0) + channel_mask |= 1; + if (strncmp(argv[2], "on", 2) == 0) + channel_mask |= 2; + + memset(&pcmd, 0, sizeof(pcmd)); + memset(&prx, 0, sizeof(prx)); + + pcmd.cmd = CMD_GET_VIM; + pcmd.user_out = channel_mask; + user_out = channel_mask; + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + + return err; +} + +static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + tx_msp_cmd pcmd; + rx_msp_cmd prx; + int err; + uchar channel_num = 0; + + if (argc < 2) + return cmd_usage(cmdtp); + + channel_num = simple_strtol(argv[1], NULL, 10); + if ((channel_num != 1) && (channel_num != 2)) { + printf("mtc digin: invalid parameter - must be '1' or '2'\n"); + return -1; + } + + memset(&pcmd, 0, sizeof(pcmd)); + memset(&prx, 0, sizeof(prx)); + + pcmd.cmd = CMD_GET_VIM; + pcmd.user_out = user_out; + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + + if (!err) { + /* function returns '0' when digin is on */ + err = (prx.input & channel_num) ? 0 : 1; + } + + return err; +} + +static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + tx_msp_cmd pcmd; + rx_msp_cmd prx; + int err; + char buf[5]; + uchar appreg; + + /* read appreg */ + memset(&pcmd, 0, sizeof(pcmd)); + memset(&prx, 0, sizeof(prx)); + + pcmd.cmd = CMD_WD_PARA; + pcmd.cmd_val0 = 5; /* max. Count */ + pcmd.cmd_val1 = 5; /* max. Time */ + pcmd.cmd_val2 = 0; /* =0 means read appreg */ + pcmd.user_out = user_out; + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + + /* on success decide between read or write */ + if (!err) { + if (argc == 2) { + appreg = simple_strtol(argv[1], NULL, 10); + if (appreg == 0) { + printf("mtc appreg: invalid parameter - " + "must be between 1 and 255\n"); + return -1; + } + memset(&pcmd, 0, sizeof(pcmd)); + pcmd.cmd = CMD_WD_PARA; + pcmd.cmd_val0 = prx.ack3; /* max. Count */ + pcmd.cmd_val1 = prx.ack0; /* max. Time */ + pcmd.cmd_val2 = appreg; /* !=0 means write appreg */ + pcmd.user_out = user_out; + memset(&prx, 0, sizeof(prx)); + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + } else { + sprintf(buf, "%d", prx.ack2); + setenv("appreg", buf); + } + } + + return err; +} + +static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + tx_msp_cmd pcmd; + rx_msp_cmd prx; + int err; + + memset(&pcmd, 0, sizeof(pcmd)); + memset(&prx, 0, sizeof(prx)); + + pcmd.cmd = CMD_FW_VERSION; + pcmd.user_out = user_out; + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + + if (!err) { + printf("FW V%d.%d.%d / HW %d\n", + prx.ack0, prx.ack1, prx.ack3, prx.ack2); + } + + return err; +} + +static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + tx_msp_cmd pcmd; + rx_msp_cmd prx; + int err; + + memset(&pcmd, 0, sizeof(pcmd)); + memset(&prx, 0, sizeof(prx)); + + pcmd.cmd = CMD_WD_WDSTATE; + pcmd.cmd_val2 = 1; + pcmd.user_out = user_out; + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + + if (!err) { + printf("State %02Xh\n", prx.state); + printf("Input %02Xh\n", prx.input); + printf("UserWD %02Xh\n", prx.ack2); + printf("Sys WD %02Xh\n", prx.ack3); + printf("WD Timout %02Xh\n", prx.ack0); + printf("eSysState %02Xh\n", prx.ack1); + } + + return err; +} + +static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); + +cmd_tbl_t cmd_mtc_sub[] = { + U_BOOT_CMD_MKENT(led, 3, 1, do_mtc_led, + "set state of leds", + "[ledname] [state] [blink]\n" + " - lednames: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n" + " - state: off red green orange\n" + " - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"), + U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key, + "returns state of user key", ""), + U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version, + "returns firmware version of supervisor uC", ""), + U_BOOT_CMD_MKENT(appreg, 1, 1, do_mtc_appreg, + "reads or writes appreg value and stores in environment " + "variable 'appreg'", + "[value] - value (1 - 255) to write to appreg"), + U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin, + "returns state of digital input", + "<channel_num> - get state of digital input (1 or 2)\n"), + U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout, + "sets digital outputs", + "<on|off> <on|off>- set state of digital output 1 and 2\n"), + U_BOOT_CMD_MKENT(state, 0, 1, do_mtc_state, + "displays state", ""), + U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help", + "[command] - get help for command\n"), +}; + +static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + extern int _do_help(cmd_tbl_t *cmd_start, int cmd_items, + cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]); +#ifdef CONFIG_SYS_LONGHELP + puts("mtc "); +#endif + return _do_help(&cmd_mtc_sub[0], + ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv); +} + +int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *c; + int err = 0; + + c = find_cmd_tbl(argv[1], &cmd_mtc_sub[0], ARRAY_SIZE(cmd_mtc_sub)); + if (c) { + argc--; + argv++; + return c->cmd(c, flag, argc, argv); + } else { + /* Unrecognized command */ + return cmd_usage(cmdtp); + } + + return err; +} + +U_BOOT_CMD(mtc, 5, 1, cmd_mtc, + "special commands for digsyMTC", + "[subcommand] [args...]\n" + "Subcommands list:\n" + "led [ledname] [state] [blink] - set state of leds\n" + " [ledname]: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n" + " [state]: off red green orange\n" + " [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n" + "key - returns state of user key\n" + "version - returns firmware version of supervisor uC\n" + "appreg [value] - reads (in environment variable 'appreg') or writes" + " appreg value\n" + " [value]: value (1 - 255) to write to appreg\n" + "digin [channel] - returns state of digital input (1 or 2)\n" + "digout <on|off> <on|off> - sets state of two digital outputs\n" + "state - displays state\n" + "help [subcommand] - get help for subcommand\n" +); diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.h b/board/intercontrol/digsy_mtc/cmd_mtc.h new file mode 100644 index 0000000..81714e3 --- /dev/null +++ b/board/intercontrol/digsy_mtc/cmd_mtc.h @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2009 + * Werner Pfister <Pfister_Werner@intercontrol.de> + * + * (C) Copyright 2009 Semihalf, Grzegorz Bernacki + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef CMD_MTC_H +#define CMD_MTC_H + +#define CMD_WD_PARA 0x02 +#define CMD_WD_WDSTATE 0x04 +#define CMD_FW_VERSION 0x10 +#define CMD_GET_VIM 0x30 +#define CMD_SET_LED 0x40 + +typedef struct { + u8 cmd; + u8 sys_in; + u8 cmd_val0; + u8 cmd_val1; + u8 cmd_val2; + u8 user_out; + u8 cks; + u8 dummy1; + u8 dummy2; +} tx_msp_cmd; + +typedef struct { + u8 input; + u8 state; + u8 ack2; + u8 ack3; + u8 ack0; + u8 ack1; + u8 ack; + u8 dummy; + u8 cks; +} rx_msp_cmd; + +#define MTC_TRANSFER_SIZE (sizeof(tx_msp_cmd) * 8) + +#endif diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c new file mode 100644 index 0000000..784ba2a --- /dev/null +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -0,0 +1,500 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2005-2009 + * Modified for InterControl digsyMTC MPC5200 board by + * Frank Bodammer, GCD Hard- & Software GmbH, + * frank.bodammer@gcd-solutions.de + * + * (C) Copyright 2009 + * Grzegorz Bernacki, Semihalf, gjb@semihalf.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <net.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "eeprom.h" +#if defined(CONFIG_DIGSY_REV5) +#include "is45s16800a2.h" +#include <mtd/cfi_flash.h> +#include <flash.h> +#else +#include "is42s16800a-7t.h" +#endif +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern int usb_cpu_init(void); + +#if defined(CONFIG_DIGSY_REV5) +/* + * The M29W128GH needs a specail reset command function, + * details see the doc/README.cfi file + */ +void flash_cmd_reset(flash_info_t *info) +{ + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); +} +#endif + +#ifndef CONFIG_SYS_RAMBOOT +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + long control = SDRAM_CONTROL | hi_addr_bit; + + /* unlock mode register */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); + + /* precharge all banks */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); + + /* auto refresh */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); + + /* set mode register */ + out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); + + /* normal operation */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if + * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. + */ + +phys_size_t initdram(int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; +#ifndef CONFIG_SYS_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */ + out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ + + /* setup config registers */ + out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); + out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); + sdram_start(1); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, + (0x13 + __builtin_ffs(dramsize >> 20) - 1)); + } else { + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C); + + /* find RAM size using SDRAM CS1 only */ + test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), + 0x08000000); + dramsize2 = test1; + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) + dramsize2 = 0; + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize | + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); + } else { + out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */ + } + +#else /* CONFIG_SYS_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CONFIG_SYS_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) + out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); + + return dramsize + dramsize2; +} + +int checkboard(void) +{ + char buf[64]; + int i = getenv_f("serial#", buf, sizeof(buf)); + + puts ("Board: InterControl digsyMTC"); +#if defined(CONFIG_DIGSY_REV5) + puts (" rev5"); +#endif + if (i > 0) { + puts(", "); + puts(buf); + } + putc('\n'); + + return 0; +} + +#if defined(CONFIG_VIDEO) + +#define GPIO_USB1_0 0x00010000 /* Power-On pin */ +#define GPIO_USB1_9 0x08 /* PX_~EN pin */ + +#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */ +#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */ +#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */ +#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */ + +#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */ + +/* ExBo I2C Addresses */ +#define EXBO_EE_I2C_ADDRESS 0x56 + +static void exbo_hw_init(void) +{ + struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + unsigned char val; + + /* 1st, check if extension board is present */ + if (i2c_read(EXBO_EE_I2C_ADDRESS, 0, 1, &val, 1)) + return; + + /* configure IrDA pins (PSC6 port) as gpios */ + gpio->port_config &= 0xFF8FFFFF; + + /* Init for USB1_0, EE_CLK and EE_DI - Low */ + setbits_be32(&gpio->simple_ddr, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + clrbits_be32(&gpio->simple_ode, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + clrbits_be32(&gpio->simple_dvo, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + setbits_be32(&gpio->simple_gpioe, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + + /* Init for EE_DO, EE_CTS - Input */ + clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS); + setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS); + + /* Init for PX_~EN (USB1_9) - High */ + clrbits_8(&gpio->sint_ode, GPIO_USB1_9); + setbits_8(&gpio->sint_ddr, GPIO_USB1_9); + clrbits_8(&gpio->sint_inten, GPIO_USB1_9); + setbits_8(&gpio->sint_dvo, GPIO_USB1_9); + setbits_8(&gpio->sint_gpioe, GPIO_USB1_9); + + /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */ + out_be32(&gpt[0].emsr, GPT_GPIO_ON); + /* Init for S Switch (GPIO4) - Timer_1 GPIO High */ + out_be32(&gpt[1].emsr, GPT_GPIO_ON); + + /* Power-On camera supply */ + setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); +} +#else +static inline void exbo_hw_init(void) {} +#endif /* CONFIG_VIDEO */ + +int board_early_init_r(void) +{ +#ifdef CONFIG_MPC52XX_SPI + struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT; +#endif + /* + * Now, when we are in RAM, enable flash write access for detection + * process. Note that CS_BOOT cannot be cleared when executing in + * flash. + */ + /* disable CS_BOOT */ + clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); + /* enable CS1 */ + setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17)); + /* enable CS0 */ + setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); + + exbo_hw_init(); + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) + /* Low level USB init, required for proper kernel operation */ + usb_cpu_init(); +#endif +#ifdef CONFIG_MPC52XX_SPI + /* GPT 6 Output Enable */ + out_be32(&gpt[6].emsr, 0x00000034); + /* GPT 7 Output Enable */ + out_be32(&gpt[7].emsr, 0x00000034); +#endif + + return (0); +} + +void board_get_enetaddr (uchar * enet) +{ + ushort read = 0; + ushort addr_of_eth_addr = 0; + ushort len_sys = 0; + ushort len_sys_cfg = 0; + + /* check identification word */ + eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2); + if (read != EEPROM_IDENT) + return; + + /* calculate offset of config area */ + eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2); + eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG, + (uchar *)&len_sys_cfg, 2); + addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1; + if (addr_of_eth_addr >= EEPROM_LEN) + return; + + eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6); +} + +int misc_init_r(void) +{ + uchar enetaddr[6]; + + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + board_get_enetaddr(enetaddr); + eth_setenv_enetaddr("ethaddr", enetaddr); + } + + return 0; +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#ifdef CONFIG_CMD_IDE + +#ifdef CONFIG_IDE_RESET + +void init_ide_reset(void) +{ + debug ("init_ide_reset\n"); + + /* set gpio output value to 1 */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); + /* open drain output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); + /* direction output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); + /* enable gpio */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); + +} + +void ide_set_reset(int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + + /* set gpio output value to 0 */ + clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); + /* open drain output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); + /* direction output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); + /* enable gpio */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); + + udelay(10000); + + /* set gpio output value to 1 */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); + /* open drain output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); + /* direction output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); + /* enable gpio */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); +} +#endif /* CONFIG_IDE_RESET */ +#endif /* CONFIG_CMD_IDE */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +static void ft_delete_node(void *fdt, const char *compat) +{ + int off = -1; + int ret; + + off = fdt_node_offset_by_compatible(fdt, -1, compat); + if (off < 0) { + printf("Could not find %s node.\n", compat); + return; + } + + ret = fdt_del_node(fdt, off); + if (ret < 0) + printf("Could not delete %s node.\n", compat); +} +#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) +static void ft_adapt_flash_base(void *blob) +{ + flash_info_t *dev = &flash_info[0]; + int off; + struct fdt_property *prop; + int len; + u32 *reg, *reg2; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb"); + if (off < 0) { + printf("Could not find fsl,mpc5200b-lpb node.\n"); + return; + } + + /* found compatible property */ + prop = fdt_get_property_w(blob, off, "ranges", &len); + if (prop) { + reg = reg2 = (u32 *)&prop->data[0]; + + reg[2] = dev->start[0]; + reg[3] = dev->size; + fdt_setprop(blob, off, "ranges", reg2, len); + } else + printf("Could not find ranges\n"); +} + +extern ulong flash_get_size (phys_addr_t base, int banknum); + +/* Update the Flash Baseaddr settings */ +int update_flash_size (int flash_size) +{ + volatile struct mpc5xxx_mmap_ctl *mm = + (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; + flash_info_t *dev; + int i; + int size = 0; + unsigned long base = 0x0; + u32 *cs_reg = (u32 *)&mm->cs0_start; + + for (i = 0; i < 2; i++) { + dev = &flash_info[i]; + + if (dev->size) { + /* calculate new base addr for this chipselect */ + base -= dev->size; + out_be32(cs_reg, START_REG(base)); + cs_reg++; + out_be32(cs_reg, STOP_REG(base, dev->size)); + cs_reg++; + /* recalculate the sectoraddr in the cfi driver */ + size += flash_get_size(base, i); + } + } + flash_protect_default(); + gd->bd->bi_flashstart = base; + return 0; +} +#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ + +void ft_board_setup(void *blob, bd_t *bd) +{ + int phy_addr = CONFIG_PHY_ADDR; + char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; + + ft_cpu_setup(blob, bd); + /* + * There are 2 RTC nodes in the DTS, so remove + * the unneeded node here. + */ +#if defined(CONFIG_DIGSY_REV5) + ft_delete_node(blob, "dallas,ds1339"); +#else + ft_delete_node(blob, "mc,rv3029c2"); +#endif +#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) +#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE + /* Update reg property in all nor flash nodes too */ + fdt_fixup_nor_flash_size(blob); +#endif + ft_adapt_flash_base(blob); +#endif + /* fix up the phy address */ + do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h new file mode 100644 index 0000000..39e0378 --- /dev/null +++ b/board/intercontrol/digsy_mtc/eeprom.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2009 Semihalf. + * Written by: Grzegorz Bernacki <gjb@semihalf.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the anty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef CMD_EEPROM_H +#define CMD_EEPROM_H + +#define EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR +#define EEPROM_LEN 1024 /* eeprom length */ +#define EEPROM_IDENT 2408 /* identification word */ +#define EEPROM_ADDR_IDENT 0 /* identification word offset */ +#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */ +#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */ +#define EEPROM_ADDR_ETHADDR 23 /* ethernet addres offset */ + +#endif diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h new file mode 100644 index 0000000..64a81f4 --- /dev/null +++ b/board/intercontrol/digsy_mtc/is42s16800a-7t.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2004-2009 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x505F0000 +#define SDRAM_CONFIG1 0xD2322900 +#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h new file mode 100644 index 0000000..6ab5c12 --- /dev/null +++ b/board/intercontrol/digsy_mtc/is45s16800a2.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * based on: + * (C) Copyright 2004-2009 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x50470000 +#define SDRAM_CONFIG1 0xD2322900 +#define SDRAM_CONFIG2 0x8AD70000 |