summaryrefslogtreecommitdiff
path: root/board/innokom
diff options
context:
space:
mode:
Diffstat (limited to 'board/innokom')
-rw-r--r--board/innokom/flash.c18
-rw-r--r--board/innokom/lowlevel_init.S66
2 files changed, 42 insertions, 42 deletions
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
index 7f17ba6..8c95341 100644
--- a/board/innokom/flash.c
+++ b/board/innokom/flash.c
@@ -72,7 +72,7 @@
#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */
#endif
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/**
* flash_init: - initialize data structures for flash chips
@@ -85,14 +85,14 @@ ulong flash_init(void)
int i, j;
ulong size = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(INTEL_MANUFACT & FLASH_VENDMASK) |
(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
switch (i) {
case 0:
@@ -110,8 +110,8 @@ ulong flash_init(void)
/* Protect u-boot sectors */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE + (256*1024) - 1,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + (256*1024) - 1,
&flash_info[0]);
#ifdef CONFIG_ENV_IS_IN_FLASH
@@ -135,7 +135,7 @@ void flash_print_info (flash_info_t *info)
{
int i, j;
- for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
+ for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
switch (info->flash_id & FLASH_VENDMASK) {
@@ -235,7 +235,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
while ((*addr & 0x0080) != 0x0080) {
PRINTK(".");
- if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B0; /* suspend erase*/
*addr = 0x00FF; /* read mode */
rc = ERR_TIMOUT;
@@ -306,7 +306,7 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
/* wait while polling the status register */
while(((val = *addr) & 0x80) != 0x80) {
- if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
*addr = 0xB0; /* suspend program command */
goto outahere;
diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S
index 4c9f10f..9892430 100644
--- a/board/innokom/lowlevel_init.S
+++ b/board/innokom/lowlevel_init.S
@@ -29,7 +29,7 @@
#include <version.h>
#include <asm/arch/pxa-regs.h>
-DRAM_SIZE: .long CFG_DRAM_SIZE
+DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
@@ -54,71 +54,71 @@ lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
+ ldr r1, =CONFIG_SYS_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
+ ldr r1, =CONFIG_SYS_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
+ ldr r1, =CONFIG_SYS_GPSR2_VAL
str r1, [r0]
ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
+ ldr r1, =CONFIG_SYS_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
+ ldr r1, =CONFIG_SYS_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
+ ldr r1, =CONFIG_SYS_GPCR2_VAL
str r1, [r0]
ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
+ ldr r1, =CONFIG_SYS_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
+ ldr r1, =CONFIG_SYS_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
+ ldr r1, =CONFIG_SYS_GPDR2_VAL
str r1, [r0]
ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
+ ldr r1, =CONFIG_SYS_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
+ ldr r1, =CONFIG_SYS_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
+ ldr r1, =CONFIG_SYS_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
+ ldr r1, =CONFIG_SYS_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
+ ldr r1, =CONFIG_SYS_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
+ ldr r1, =CONFIG_SYS_GAFR2_U_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
+ ldr r1, =CONFIG_SYS_PSSR_VAL
str r1, [r0]
/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
+/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
/* */
@@ -168,17 +168,17 @@ mem_init:
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
+ ldr r2, =CONFIG_SYS_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
+ ldr r2, =CONFIG_SYS_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
+ ldr r2, =CONFIG_SYS_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
@@ -187,37 +187,37 @@ mem_init:
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
+ ldr r2, =CONFIG_SYS_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
+ ldr r2, =CONFIG_SYS_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
+ ldr r2, =CONFIG_SYS_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
+ ldr r2, =CONFIG_SYS_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
+ ldr r2, =CONFIG_SYS_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
+ ldr r2, =CONFIG_SYS_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
+ ldr r2, =CONFIG_SYS_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
@@ -239,7 +239,7 @@ mem_init:
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
- ldr r3, =CFG_MDREFR_VAL
+ ldr r3, =CONFIG_SYS_MDREFR_VAL
ldr r2, =0xFFF
and r3, r3, r2
ldr r4, =0x03ca4000
@@ -269,7 +269,7 @@ mem_init:
/* Step 4a: assert MDREFR:K?RUN and configure */
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
- ldr r4, =CFG_MDREFR_VAL
+ ldr r4, =CONFIG_SYS_MDREFR_VAL
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
@@ -292,7 +292,7 @@ mem_init:
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
- ldr r4, =CFG_MDCNFG_VAL
+ ldr r4, =CONFIG_SYS_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
@@ -325,7 +325,7 @@ mem_init:
/* Jan 2003, Errata #116, page 30. */
- ldr r3, =CFG_DRAM_BASE
+ ldr r3, =CONFIG_SYS_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
@@ -345,7 +345,7 @@ mem_init:
/* Step 4h: Write MDMRS. */
- ldr r2, =CFG_MDMRS_VAL
+ ldr r2, =CONFIG_SYS_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
generated by cgit v1.1 at 2024-11-25 19:50:33 +0000