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-rw-r--r--board/imgtec/malta/lowlevel_init.S164
-rw-r--r--board/imgtec/malta/malta.c126
2 files changed, 281 insertions, 9 deletions
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index fa0b6a7..1af34f1 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -6,6 +6,8 @@
#include <config.h>
#include <gt64120.h>
+#include <msc01.h>
+#include <pci.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
@@ -25,6 +27,25 @@
.globl lowlevel_init
lowlevel_init:
+ /* detect the core card */
+ li t0, KSEG1ADDR(MALTA_REVISION)
+ lw t0, 0(t0)
+ srl t0, t0, MALTA_REVISION_CORID_SHF
+ andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
+ MALTA_REVISION_CORID_SHF)
+
+ /* core cards using the gt64120 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_LV
+ beq t0, t1, _gt64120
+
+ /* core cards using the MSC01 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_FPGA6
+ beq t0, t1, _msc01
+ nop
+
+ /* unknown system controller */
+ b .
+ nop
/*
* Load BAR registers of GT64120 as done by YAMON
@@ -39,7 +60,7 @@ lowlevel_init:
* based on write_bootloader() in qemu.git/hw/mips_malta.c
* see GT64120 manual and qemu.git/hw/gt64xxx.c for details
*/
-
+_gt64120:
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
li t1, KSEG1ADDR(GT_DEF_BASE)
li t0, CPU_TO_GT32(0xdf000000)
@@ -67,3 +88,144 @@ lowlevel_init:
jr ra
nop
+
+ /*
+ *
+ */
+_msc01:
+ /* setup peripheral bus controller clock divide */
+ li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+ li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
+ sw t1, MSC01_PBC_CLKCFG_OFS(t0)
+
+ /* tweak peripheral bus controller timings */
+ li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
+ (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
+ sw t1, MSC01_PBC_CS0TIM_OFS(t0)
+ li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
+ (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
+ sw t1, MSC01_PBC_CS0RW_OFS(t0)
+ lw t1, MSC01_PBC_CS0CFG_OFS(t0)
+ li t2, MSC01_PBC_CS0CFG_DTYP_MSK
+ and t1, t2
+ ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
+ (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
+ (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
+ sw t1, MSC01_PBC_CS0CFG_OFS(t0)
+
+ /* setup basic address decode */
+ li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+ li t1, 0x0
+ li t2, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
+ sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
+
+ /* initialise IP1 - unused */
+ li t1, MALTA_MSC01_IP1_BASE
+ li t2, -MALTA_MSC01_IP1_SIZE
+ sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
+
+ /* initialise IP2 - PCI */
+ li t1, MALTA_MSC01_IP2_BASE1
+ li t2, -MALTA_MSC01_IP2_SIZE1
+ sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
+ li t1, MALTA_MSC01_IP2_BASE2
+ li t2, -MALTA_MSC01_IP2_SIZE2
+ sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
+
+ /* initialise IP3 - peripheral bus controller */
+ li t1, MALTA_MSC01_IP3_BASE
+ li t2, -MALTA_MSC01_IP3_SIZE
+ sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
+
+ /* setup PCI memory */
+ li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+ li t1, MALTA_MSC01_PCIMEM_BASE
+ li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIMEM_MAP
+ sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
+
+ /* setup PCI I/O */
+ li t1, MALTA_MSC01_PCIIO_BASE
+ li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIIO_MAP
+ sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
+
+ /* setup PCI_BAR0 memory window */
+ li t1, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_PCI_BAR0_OFS(t0)
+
+ /* setup PCI to SysCon/CPU translation */
+ sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
+ sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
+
+ /* setup PCI vendor & device IDs */
+ li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
+ (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
+ sw t1, MSC01_PCI_HEAD0_OFS(t0)
+
+ /* setup PCI subsystem vendor & device IDs */
+ sw t1, MSC01_PCI_HEAD11_OFS(t0)
+
+ /* setup PCI class, revision */
+ li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
+ (0x1 << MSC01_PCI_HEAD2_REV_SHF)
+ sw t1, MSC01_PCI_HEAD2_OFS(t0)
+
+ /* ensure a sane setup */
+ sw zero, MSC01_PCI_HEAD3_OFS(t0)
+ sw zero, MSC01_PCI_HEAD4_OFS(t0)
+ sw zero, MSC01_PCI_HEAD5_OFS(t0)
+ sw zero, MSC01_PCI_HEAD6_OFS(t0)
+ sw zero, MSC01_PCI_HEAD7_OFS(t0)
+ sw zero, MSC01_PCI_HEAD8_OFS(t0)
+ sw zero, MSC01_PCI_HEAD9_OFS(t0)
+ sw zero, MSC01_PCI_HEAD10_OFS(t0)
+ sw zero, MSC01_PCI_HEAD12_OFS(t0)
+ sw zero, MSC01_PCI_HEAD13_OFS(t0)
+ sw zero, MSC01_PCI_HEAD14_OFS(t0)
+ sw zero, MSC01_PCI_HEAD15_OFS(t0)
+
+ /* setup PCI command register */
+ li t1, (PCI_COMMAND_FAST_BACK | \
+ PCI_COMMAND_SERR | \
+ PCI_COMMAND_PARITY | \
+ PCI_COMMAND_MASTER | \
+ PCI_COMMAND_MEMORY)
+ sw t1, MSC01_PCI_HEAD1_OFS(t0)
+
+ /* setup PCI byte swapping */
+#ifdef CONFIG_SYS_BIG_ENDIAN
+ li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
+ (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
+ sw t1, MSC01_PCI_SWAP_OFS(t0)
+#else
+ sw zero, MSC01_PCI_SWAP_OFS(t0)
+#endif
+
+ /* enable PCI host configuration cycles */
+ lw t1, MSC01_PCI_CFG_OFS(t0)
+ li t2, MSC01_PCI_CFG_RA_MSK | \
+ MSC01_PCI_CFG_G_MSK | \
+ MSC01_PCI_CFG_EN_MSK
+ or t1, t1, t2
+ sw t1, MSC01_PCI_CFG_OFS(t0)
+
+ jr ra
+ nop
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 09da9ea..2af0067 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -1,19 +1,67 @@
/*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <netdev.h>
+#include <pci_gt64120.h>
+#include <pci_msc01.h>
+#include <serial.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/malta.h>
-#include <pci_gt64120.h>
#include "superio.h"
+enum core_card {
+ CORE_UNKNOWN,
+ CORE_LV,
+ CORE_FPGA6,
+};
+
+enum sys_con {
+ SYSCON_UNKNOWN,
+ SYSCON_GT64120,
+ SYSCON_MSC01,
+};
+
+static enum core_card malta_core_card(void)
+{
+ u32 corid, rev;
+
+ rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+ corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
+
+ switch (corid) {
+ case MALTA_REVISION_CORID_CORE_LV:
+ return CORE_LV;
+
+ case MALTA_REVISION_CORID_CORE_FPGA6:
+ return CORE_FPGA6;
+
+ default:
+ return CORE_UNKNOWN;
+ }
+}
+
+static enum sys_con malta_sys_con(void)
+{
+ switch (malta_core_card()) {
+ case CORE_LV:
+ return SYSCON_GT64120;
+
+ case CORE_FPGA6:
+ return SYSCON_MSC01;
+
+ default:
+ return SYSCON_UNKNOWN;
+ }
+}
+
phys_size_t initdram(int board_type)
{
return CONFIG_SYS_MEM_SIZE;
@@ -21,7 +69,25 @@ phys_size_t initdram(int board_type)
int checkboard(void)
{
- puts("Board: MIPS Malta CoreLV (Qemu)\n");
+ enum core_card core;
+
+ puts("Board: MIPS Malta");
+
+ core = malta_core_card();
+ switch (core) {
+ case CORE_LV:
+ puts(" CoreLV");
+ break;
+
+ case CORE_FPGA6:
+ puts(" CoreFPGA6");
+ break;
+
+ default:
+ puts(" CoreUnknown");
+ }
+
+ putc('\n');
return 0;
}
@@ -40,18 +106,62 @@ void _machine_restart(void)
int board_early_init_f(void)
{
+ void *io_base;
+
+ /* choose correct PCI I/O base */
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+ break;
+
+ case SYSCON_MSC01:
+ io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+ break;
+
+ default:
+ return -1;
+ }
+
/* setup FDC37M817 super I/O controller */
- malta_superio_init((void *)CKSEG1ADDR(MALTA_IO_PORT_BASE));
+ malta_superio_init(io_base);
return 0;
}
+struct serial_device *default_serial_console(void)
+{
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ return &eserial1_device;
+
+ default:
+ case SYSCON_MSC01:
+ return &eserial2_device;
+ }
+}
+
void pci_init_board(void)
{
- set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
+
+ gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ 0x10000000, 0x10000000, 128 * 1024 * 1024,
+ 0x00000000, 0x00000000, 0x20000);
+ break;
+
+ default:
+ case SYSCON_MSC01:
+ set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
- gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- 0x10000000, 0x10000000, 128 * 1024 * 1024,
- 0x00000000, 0x00000000, 0x20000);
+ msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ MALTA_MSC01_PCIMEM_MAP,
+ CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
+ MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
+ 0x00000000, MALTA_MSC01_PCIIO_SIZE);
+ break;
+ }
}
generated by cgit v1.1 at 2024-07-04 21:28:23 +0000