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-rw-r--r--board/ids8247/ids8247.c92
1 files changed, 84 insertions, 8 deletions
diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c
index 68b7070..79fe9da 100644
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -304,21 +304,97 @@ phys_size_t initdram (int board_type)
int misc_init_r (void)
{
gd->bd->bi_flashstart = 0xff800000;
+ return 0;
}
#if defined(CONFIG_CMD_NAND)
-extern ulong
-nand_probe (ulong physadr);
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <asm/io.h>
+
+static u8 hwctl;
+
+static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE ) {
+ hwctl |= 0x1;
+ writeb(0x00, (this->IO_ADDR_W + 0x0a));
+ } else {
+ hwctl &= ~0x1;
+ writeb(0x00, (this->IO_ADDR_W + 0x08));
+ }
+ if ( ctrl & NAND_ALE ) {
+ hwctl |= 0x2;
+ writeb(0x00, (this->IO_ADDR_W + 0x09));
+ } else {
+ hwctl &= ~0x2;
+ writeb(0x00, (this->IO_ADDR_W + 0x08));
+ }
+ if ( (ctrl & NAND_NCE) != NAND_NCE)
+ writeb(0x00, (this->IO_ADDR_W + 0x0c));
+ else
+ writeb(0x00, (this->IO_ADDR_W + 0x08));
+ }
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+
+}
-void
-nand_init (void)
+static u_char ids_nand_read_byte(struct mtd_info *mtd)
{
- ulong totlen = 0;
+ struct nand_chip *this = mtd->priv;
- debug ("Probing at 0x%.8x\n", CONFIG_SYS_NAND0_BASE);
- totlen += nand_probe (CONFIG_SYS_NAND0_BASE);
+ return readb(this->IO_ADDR_R);
+}
+
+static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ writeb(buf[i], (nand->IO_ADDR_W + 0x02));
+ else if (hwctl & 0x2)
+ writeb(buf[i], (nand->IO_ADDR_W + 0x01));
+ else
+ writeb(buf[i], nand->IO_ADDR_W);
+ }
+}
- printf ("%4lu MB\n", totlen >>20);
+static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct nand_chip *this = mtd->priv;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ buf[i] = readb(this->IO_ADDR_R);
+ }
+}
+
+static int ids_nand_dev_ready(struct mtd_info *mtd)
+{
+ /* constant delay (see also tR in the datasheet) */
+ udelay(12);
+ return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->ecc.mode = NAND_ECC_SOFT;
+
+ /* Reference hardware control function */
+ nand->cmd_ctrl = ids_nand_hwctrl;
+ nand->read_byte = ids_nand_read_byte;
+ nand->write_buf = ids_nand_write_buf;
+ nand->read_buf = ids_nand_read_buf;
+ nand->dev_ready = ids_nand_dev_ready;
+ nand->chip_delay = 12;
+
+ return 0;
}
#endif /* CONFIG_CMD_NAND */