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-rw-r--r--board/icecube/icecube.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 44831c6..4197a7c 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <asm/processor.h>
#if defined(CONFIG_LITE5200B)
#include "mt46v32m16.h"
@@ -89,6 +90,8 @@ long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
+ uint svr, pvr;
+
#ifndef CFG_RAMBOOT
ulong test1, test2;
@@ -183,6 +186,24 @@ long int initdram (int board_type)
#endif /* CFG_RAMBOOT */
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
return dramsize + dramsize2;
}